公开(公告)号：US12125740B2

公开(公告)日：2024-10-22

申请号：US18500386

申请日：2023-11-02

Applicant: SONY GROUP CORPORATION

Inventor： Kyohei Mizuta

IPC: H01L21/768 ,  H01L21/822 ,  H01L27/04 ,  H01L27/146 ,  H04N25/57 ,  H04N25/621 ,  H04N25/76

CPC classification number: H01L21/768 ,  H01L21/822 ,  H01L27/04 ,  H01L27/146 ,  H01L27/14603 ,  H01L27/14612 ,  H01L27/14656 ,  H04N25/57 ,  H04N25/621 ,  H04N25/76

Abstract: The present technology relates to an imaging device capable of preventing a decrease of sensitivity of the imaging device in a case where a capacitance element is provided in a pixel, a method of manufacturing an imaging device, and an electronic device. The imaging device includes, in a pixel, a photoelectric conversion element and a capacitance element accumulating an electric charge generated by the photoelectric conversion element. The capacitance element includes a first electrode including a plurality of trenches, a plurality of second electrodes each having a cross-sectional area smaller than a contact connected to a gate electrode of a transistor in the pixel, and buried in each of the trenches, and a first insulating film disposed between the first electrode and the second electrode in each of the trenches. The present technology can be applied, for example, to a backside irradiation-type CMOS image sensor.

公开(公告)号：US12095440B2

公开(公告)日：2024-09-17

申请号：US17765046

申请日：2020-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuaki Ohshima ,  Hitoshi Kunitake ,  Yuto Yakubo ,  Takayuki Ikeda

IPC: H03H7/38 ,  H01L21/02 ,  H01L21/822 ,  H01L27/088 ,  H03F3/19 ,  H03F3/60

CPC classification number: H03H7/38 ,  H01L21/02565 ,  H01L21/822 ,  H01L27/088 ,  H03F3/19 ,  H03F3/60

Abstract: An amplifier is formed in a wiring layer. A semiconductor device includes a second layer over a first layer with a metal oxide therebetween. The first layer includes a first transistor including a first semiconductor layer containing silicon. The second layer includes an impedance matching circuit, and the impedance matching circuit includes a second transistor including a second semiconductor layer containing gallium. The first transistor forms first coupling capacitance between the first transistor and the metal oxide, and the impedance matching circuit forms second coupling capacitance between the impedance matching circuit and the metal oxide. The impedance matching circuit is electrically connected to the metal oxide through the second coupling capacitance. The metal oxide inhibits the influence of first radiation noise emitted from the impedance matching circuit on the operation of the first transistor.

公开(公告)号：US12080708B2

公开(公告)日：2024-09-03

申请号：US18306342

申请日：2023-04-25

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： James Joseph Brogle ,  Joseph Gerard Bukowski ,  Margaret Mary Barter ,  Timothy Edward Boles

IPC: H01L27/06 ,  H01L21/225 ,  H01L21/265 ,  H01L23/66 ,  H01L27/08 ,  H01L29/868 ,  H01L21/822 ,  H01L29/66

CPC classification number: H01L27/0676 ,  H01L21/2253 ,  H01L21/2254 ,  H01L21/26513 ,  H01L23/66 ,  H01L27/0814 ,  H01L29/868 ,  H01L21/822 ,  H01L29/6609 ,  H01L2223/6627 ,  H01L2223/6666 ,  H01L2223/6683

Abstract: A number of diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a diode limiter includes a first diode having a first doped region formed to a first depth into an intrinsic layer of a semiconductor structure, a second diode having a second doped region formed to a second depth into the intrinsic layer of the semiconductor structure, and at least one passive component. The first diode includes a first effective intrinsic region of a first thickness, the second diode includes a second effective intrinsic region of a second thickness. The first thickness is greater than the second thickness. The passive component is over the intrinsic layer and electrically coupled as part of the diode limiter.

公开(公告)号：US12007813B2

公开(公告)日：2024-06-11

申请号：US18193624

申请日：2023-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Cheng-Hao Huang

IPC: G06F1/16 ,  G09F9/30 ,  H01L21/822 ,  H10K50/84 ,  H10K71/00 ,  H10K77/10 ,  G02F1/1345 ,  H01L23/00 ,  H01L27/12 ,  H10K59/131

CPC classification number: G06F1/1652 ,  G09F9/301 ,  H01L21/822 ,  H10K50/84 ,  H10K71/00 ,  H10K77/111 ,  G02F1/13458 ,  H01L24/05 ,  H01L24/06 ,  H01L24/81 ,  H01L27/124 ,  H10K59/131

Abstract: A semiconductor device includes a substrate, conductive features on the substrate, and a passivation layer over the conductive features to define conductive pads in the respective conductive features through exposed portions of each of the conductive features. Each corner of the conductive pads is free of right angle, the substrate has a pair of long sides from a top view perspective, the shape of each of the conductive pads is a parallelogram. Each of the conductive pads has a pair of long sides and a pair of short sides from a top view perspective, a portion of the conductive pads have the long sides sloped away from a first pad density area of the substrate and toward one long side of the substrate, and the rest of the conductive pads have the long sides sloped toward the first pad density area and toward the other long side of the substrate.

公开(公告)号：US11929305B2

公开(公告)日：2024-03-12

申请号：US17532446

申请日：2021-11-22

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Klaus Diefenbeck ,  Joost Adriaan Willemen

IPC: H01L23/48 ,  H01L21/822 ,  H01L23/482 ,  H01L27/02 ,  H01L21/56

CPC classification number: H01L23/4825 ,  H01L21/822 ,  H01L27/0292 ,  H01L21/56 ,  H01L27/0255

Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.

公开(公告)号：US20240056074A1

公开(公告)日：2024-02-15

申请号：US18496909

申请日：2023-10-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： TZUNG-YO HUNG ,  PIN-DAI SUE ,  CHIEN-CHI TIEN ,  TING-WEI CHIANG

IPC: H03K17/687 ,  H03K19/0948 ,  G05F3/16 ,  H03K19/0185 ,  H01L21/02 ,  H01L21/283 ,  H01L21/822 ,  H01L29/423 ,  H01L29/06

CPC classification number: H03K17/6872 ,  H03K19/0948 ,  G05F3/16 ,  H03K19/018571 ,  H01L21/02104 ,  H01L21/283 ,  H01L21/822 ,  H01L29/42312 ,  H01L29/0669 ,  B82Y10/00

Abstract: An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first control signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.

公开(公告)号：US20230378008A1

公开(公告)日：2023-11-23

申请号：US17951161

申请日：2022-09-23

Applicant: CHANGZHOU GALAXY CENTURY MICROELECTRONICS CO., LTD

Inventor： Yueyun WANG

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/822

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/822

Abstract: A chip scale package process includes: forming a groove on an upper surface of a multi-device wafer; forming a passivation layer on the upper surface and in the groove; forming an opening of the passivation layer; forming a metal bump in the opening; adding a protective layer on the upper surface and in the groove; conducting a treatment after adding the protective layer on the upper surface and in the groove to expose the metal bump; attaching a carrier to the upper surface and grinding a lower surface of the wafer to penetrate a bottom of the groove; and forming a metal layer on the lower surface and separating the carrier from the wafer to form multiple packaged devices. The CSP process avoids the need for a multi-cut process on the surface of the wafer, thereby simplifying the technological process, reducing the production cost, and improving the processing efficiency.

公开(公告)号：US11764061B2

公开(公告)日：2023-09-19

申请号：US17529130

申请日：2021-11-17

Applicant: Applied Materials, Inc.

Inventor： Wenguang Li ,  James S. Papanu

IPC: H01L21/027 ,  H01L21/3065 ,  H01L21/78 ,  H01L21/308 ,  H01L21/822

CPC classification number: H01L21/0275 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/30655 ,  H01L21/78 ,  H01L21/822

Abstract: Water soluble organic-inorganic hybrid masks and mask formulations, and methods of dicing semiconductor wafers are described. In an example, a mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. A p-block metal compound, an s-block metal compound, or a transition metal compound is dissolved throughout the water-soluble matrix.

公开(公告)号：US20230245992A1

公开(公告)日：2023-08-03

申请号：US18081248

申请日：2022-12-14

Applicant: STMicroelectronics PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/822 ,  H01L21/56

CPC classification number: H01L24/24 ,  H01L23/49805 ,  H01L21/822 ,  H01L21/565 ,  H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/19 ,  H01L2224/24226 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/73209 ,  H01L2224/16227 ,  H01L2924/182

Abstract: An integrated circuit die includes a semiconductor substrate, an interconnect layer including bonding pads, and a passivation layer covering the interconnect layer and including openings at the bonding pads. A conductive redistribution layer including conductive lines and conductive vias is supported by the passivation layer. An insulating layer covers the conductive redistribution layer and the passivation layer. Channels formed in an upper surface of the insulating layer delimit pedestal regions in the insulating layer. A through via extends from an upper surface of each pedestal region through the pedestal region and the insulating layer to reach and make contact with a portion of the conductive redistribution layer. A metal pad is formed at the upper surface of each pedestal region in contact with its associated through via. The metal pads for leads of a quad-flat no-lead (QFN) type package.

公开(公告)号：US20190237459A1

公开(公告)日：2019-08-01

申请号：US16330937

申请日：2017-09-28

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： YOHEI HIURA

IPC: H01L27/02 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0292 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/823475 ,  H01L23/522 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0266 ,  H01L27/0288 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78

Abstract: The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a plasma-induced damage (PID) protection device capable of, without increasing a chip area, releasing a large PID with high efficiency and protecting an element to be protected from the PID with higher accuracy. There are provided a protection metal-oxide-semiconductor field-effect transistor (MOSFET) that includes a drain connected to a gate electrode of a MOSFET to be protected and a grounded source and protects the MOSFET to be protected from a plasma-induced damage (PID), and a dummy antenna connected to a gate electrode of the protection MOSFET, the dummy antenna turning on the protection MOSFET prior to the MOSFET to be protected due to PID charge. The present disclosure can be applied to a semiconductor device.