公开(公告)号：US20040088528A1

公开(公告)日：2004-05-06

申请号：US10623146

申请日：2003-07-17

Applicant: STMicroelectronics S.r.l.

Inventor： Santi Carlo Adamo ,  Edmondo Gangi

IPC: G06F009/00 ,  G06F009/44 ,  G06F015/00

CPC classification number: G06F9/30163

Abstract: In order to manage, in the interrupt stage, a memory stack associated with a microcontroller according to a Program Counter signal and to a Condition Code Register signal that can be contained in respective registers, a first part of memory stack is provided which comprises a register for the Program Counter signal, and a second part of memory stack consisting of a bank of memory elements equal in number to the number of bits of the Condition Code Register signal for the number of the interrupts of the microcontroller. The two parts of stack are made to function in parallel by respective stack-pointer signals.

Abstract translation: 为了在中断阶段中根据程序计数器信号管理与微控制器相关联的存储器堆栈以及可以包含在相应寄存器中的条件码寄存器信号，提供存储器堆栈的第一部分，其包括寄存器 用于程序计数器信号的存储器堆栈，以及存储器堆栈的第二部分，其由与微控制器的中断数量的条件码寄存器信号的位数相等的一组存储器元件组成。 堆叠的两个部分通过相应的堆栈指针信号并行起作用。

公开(公告)号：US20040230319A1

公开(公告)日：2004-11-18

申请号：US10783712

申请日：2004-02-20

Applicant: STMicroelectronics S.r.l.

Inventor： Orazio Musumeci ,  Santi Carlo Adamo ,  Martino Quattrocchi ,  Francesco Bombaci

IPC: G05B015/00

CPC classification number: G06F9/325 ,  G06F9/3861 ,  G06F13/24

Abstract: A microcontroller device in which complex processing procedures to be executed iteratively are implemented in a hardware manner by finite state machines, the deice including a module for managing the processing procedures and an interrupt managing module, and a set of registers for enabling interruption of execution in the module, for managing the processing procedures and transfer of control to the interrupt manager, as well as for enabling restoration of the control to the manager of the processing procedures. The registers store information regarding the type of interrupt and the state on which it intervenes. Selection information is derived from the contents of the registers to establish whether the interrupt operates on a standard instruction or else on an iterative procedure, and in order to command operation of the control unit accordingly.

Abstract translation: 一种微控制器装置，其中迭代执行的复杂处理程序以硬件方式由有限状态机实现，该模块包括用于管理处理过程的模块和一个中断管理模块，以及一组用于使执行中断的寄存器 该模块用于管理处理过程并将控制传递给中断管理器，以及用于使管理者能够恢复对处理过程的控制。 寄存器存储有关中断类型和介入状态的信息。 从寄存器的内容中导出选择信息，以确定中断是否以标准指令进行操作，或者在迭代过程中操作，并且相应地指令控制单元的操作。