Process for manufacturing an array of cells including selection bipolar junction transistors
    1.
    发明申请
    Process for manufacturing an array of cells including selection bipolar junction transistors 有权
    用于制造包括选择双极结型晶体管的单元阵列的工艺

    公开(公告)号:US20040130000A1

    公开(公告)日:2004-07-08

    申请号:US10680721

    申请日:2003-10-07

    CPC classification number: H01L29/685 H01L27/101 H01L27/24

    Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component having a terminal connected to a respective second conduction region.

    Abstract translation: 一种用于制造单元阵列的方法,包括:在第一导电类型的半导体材料的主体中注入第一导电类型的共同导电区域; 在体内在公共导电区域上形成第二导电类型和第一掺杂水平的多个有源区域区域; 在所述主体的顶部上形成具有第一和第二开口的绝缘层; 通过第一导电类型的掺杂剂将有源区域的第一部分注入第一开口,从而在有源区域中形成第一导电类型的第二导电区域; 通过第二导电类型的掺杂剂将有源区域的第二部分注入第二开口,由此形成高于第一掺杂级的第二导电类型和第二掺杂级的控制接触区; 在主体的顶部上形成多个存储部件,每个存储部件具有连接到相应的第二传导区域的端子。

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