公开(公告)号：US20040130000A1

公开(公告)日：2004-07-08

申请号：US10680721

申请日：2003-10-07

Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

Inventor： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Gastaldi ,  Loris Vendrame ,  Augusto Benvenuti ,  Tyler Lowrey

IPC: H01L027/082

CPC classification number: H01L29/685 ,  H01L27/101 ,  H01L27/24

Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component having a terminal connected to a respective second conduction region.

Abstract translation: 一种用于制造单元阵列的方法，包括：在第一导电类型的半导体材料的主体中注入第一导电类型的共同导电区域; 在体内在公共导电区域上形成第二导电类型和第一掺杂水平的多个有源区域区域; 在所述主体的顶部上形成具有第一和第二开口的绝缘层; 通过第一导电类型的掺杂剂将有源区域的第一部分注入第一开口，从而在有源区域中形成第一导电类型的第二导电区域; 通过第二导电类型的掺杂剂将有源区域的第二部分注入第二开口，由此形成高于第一掺杂级的第二导电类型和第二掺杂级的控制接触区; 在主体的顶部上形成多个存储部件，每个存储部件具有连接到相应的第二传导区域的端子。

公开(公告)号：US20020149089A1

公开(公告)日：2002-10-17

申请号：US10035006

申请日：2001-12-27

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Loris Vendrame ,  Paolo Caprara ,  Giorgio Oddone ,  Antonio Barcella

IPC: H01L029/00

CPC classification number: H01L29/7322 ,  H01L29/0813

Abstract: A transistor includes a substrate region (14) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region (13) of the first type (Pnull) of conductivity inside the substrate region (14) and adjacent to a first terminal (C) of the transistor, a well (11) of second type (N) of conductivity placed inside the substrate region (14), wherein the well (11) of second type (N) of conductivity includes at least a second contact region (12) of a second type of conductivity (Nnull) adjacent to a region of a second terminal (B) of the transistor, and a plurality of third contact regions (10) of the first type of conductivity (Pnull) adjacent to a plurality of regions of a third terminal (E1, . . . , E3) of the transistor interposed each one (10) and other (12) by proper insulating shapes (20).

Abstract translation: 晶体管包括在相同类型（P）导电性的半导体材料层中具有导电性的第一类型（P）的衬底区域（14），至少第一类型（P +）的第一接触区域（13） 在衬底区域（14）内并且与晶体管的第一端子（C）相邻的导电性，位于衬底区域（14）内部的第二类型（N）导电体的阱（11），其中阱（11） 第二类型（N）的导电性包括与晶体管的第二端子（B）的区域相邻的至少第二导电类型（N +）的第二接触区域（12）和多个第三接触区域（10） ）通过适当的绝缘形状（20）与每个（10）和另一个（12）插入的晶体管的第三端子（E1，...，E3）的多个区域相邻的第一类型的导电性（P +）） 。

公开(公告)号：US20040227527A1

公开(公告)日：2004-11-18

申请号：US10836827

申请日：2004-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Luca Bortesi ,  Loris Vendrame ,  Alessandro Bogliolo

IPC: G01R027/26

CPC classification number: G01R27/2605 ,  G01R31/026 ,  G01R31/2853

Abstract: A method and a relative test structure for measuring the coupling capacitance between two interconnect lines exploits the so-called cross-talk effect and keeps an interconnect line at a constant reference voltage. This approach addresses the problem of short-circuit currents that affect known test structures, and allows a direct measurement of the coupling capacitance between the two interconnect lines. Capacitance measurements may also be used for determining points of interruption of interconnect lines. When a line is interrupted, the measured coupling capacitance is the capacitance of a single conducting branch. The position of points of interruption of an interconnect line is determined by measuring the coupling capacitance of all segments of the line with a second conducting line.

Abstract translation: 用于测量两个互连线之间的耦合电容的方法和相对测试结构利用所谓的串扰效应，并将互连线保持在恒定的参考电压。 这种方法解决了影响已知测试结构的短路电流的问题，并且允许直接测量两条互连线之间的耦合电容。 也可以使用电容测量来确定互连线的中断点。 当线路中断时，测量的耦合电容是单个导电支路的电容。 通过用第二导线测量线的所有段的耦合电容来确定互连线的中断点的位置。