公开(公告)号：US20030223289A1

公开(公告)日：2003-12-04

申请号：US10420533

申请日：2003-04-22

Applicant: STMicroelectronics SA

Inventor： Filipe Ganivet ,  Francesco La Rosa ,  Thierry Giovinazzi

IPC: G11C029/00

CPC classification number: G11C16/30

Abstract: An electrically erasable and programmable memory includes an array of memory cells, and a distribution line linked to a receiving terminal of an external supply voltage and to a booster circuit. The distribution line provides an internal supply voltage. The distribution line is also linked to the receiving terminal through a diode or a diode circuit simulating operation of a diode. The memory includes a regulator for triggering the booster circuit when the internal supply voltage becomes lower than a threshold so as to maintain the internal supply voltage close to the threshold when the external supply voltage is too low, at least during the reading of memory cells. The diode or the diode circuit is blocked when the external supply voltage is too low.

Abstract translation: 电可擦除和可编程存储器包括存储器单元的阵列，以及连接到外部电源电压的接收端的分配线和升压电路。 配电线路提供内部电源电压。 分配线还通过模拟二极管的操作的二极管或二极管电路与接收端相连。 存储器包括用于当内部电源电压变得低于阈值时触发升压电路的稳压器，以便至少在读取存储器单元期间，当外部电源电压太低时，内部电源电压保持接近阈值。 当外部电源电压太低时，二极管或二极管电路被阻塞。

公开(公告)号：US20040070430A1

公开(公告)日：2004-04-15

申请号：US10641337

申请日：2003-08-14

Applicant: STMicroelectronics SA

Inventor： Francesco La Rosa

IPC: H03L007/00

CPC classification number: H03K17/223

Abstract: A power on reset circuit (POR) includes a first reset circuit for delivering a first reset signal when a supply voltage of the POR circuit is between a first low threshold and a first high threshold, and a second reset circuit for delivering a second reset signal when the supply voltage is between a second low threshold and a second high threshold. The second high threshold is less than the first high threshold. The POR circuit further includes at least one electrically erasable and programmable non-volatile memory cell. A delivery circuit outputs the first reset signal or the second reset based upon on whether the at least one electrically erasable and programmable non-volatile memory cell is in an erased or programmed state. The POR circuit has a threshold for outputting the first or second reset signal that is programmable according to the intended application.

Abstract translation: 上电复位电路（POR）包括第一复位电路，用于当POR电路的电源电压处于第一低阈值和第一高阈值之间时传送第一复位信号;以及第二复位电路，用于传送第二复位信号 当电源电压处于第二低阈值和第二高阈值之间时。 第二个高阈值小于第一个高阈值。 POR电路还包括至少一个电可擦除和可编程的非易失性存储单元。 输出电路基于至少一个电可擦除可编程非易失性存储单元是否处于擦除或编程状态来输出第一复位信号或第二复位。 POR电路具有用于输出根据预期应用可编程的第一或第二复位信号的阈值。

公开(公告)号：US20040032243A1

公开(公告)日：2004-02-19

申请号：US10420342

申请日：2003-04-22

Applicant: STMicroelectronics SA

Inventor： Filipe Ganivet ,  Francesco La Rosa ,  Thierry Giovinazzi

IPC: G05F003/16

CPC classification number: G11C16/30 ,  G05F3/262 ,  G11C5/143 ,  G11C5/147 ,  H03K17/302

Abstract: A comparator compares a first voltage applied to a first input to a second voltage applied to a second input. The comparator delivers an output signal having a first value when the second voltage is higher than the first voltage, and having a second value when the second voltage is lower than the first voltage. The comparator includes first and second PMOS transistors arranged as current mirrors. The first PMOS transistor has its source connected to the first input of the comparator for receiving the first voltage. The second PMOS transistor has its source connected to the second input of the comparator for receiving the second voltage. The output of the comparator is connected to the drain of one of the transistors.

公开(公告)号：US20030143796A1

公开(公告)日：2003-07-31

申请号：US10325609

申请日：2002-12-20

Applicant: STMicroelectronics SA

Inventor： Francesco La Rosa

IPC: H01L021/8238

CPC classification number: G05F3/262

Abstract: A current or voltage generator is integrated onto a silicon wafer and may include a first element including a first NMOS transistor having its source connected to ground through an electrical resistance, a second element including a second NMOS transistor having its source connected to ground, and a bias circuit for the first and second elements. The second element may include a voltage divider. The gate of the second NMOS transistor may be connected to a dividing node of the voltage divider, and the anode of the voltage divider may be connected to the gate of the first NMOS transistor. Both elements may be biased at an operating point corresponding to an identical temperature stability point for both elements.

Abstract translation: 电流或电压发生器被集成到硅晶片上，并且可以包括第一元件，其包括通过电阻将其源极连接到地的第一NMOS晶体管，包括其源极连接到地的第二NMOS晶体管的第二元件，以及 用于第一和第二元件的偏置电路。 第二元件可以包括分压器。 第二NMOS晶体管的栅极可以连接到分压器的分压节点，并且分压器的阳极可以连接到第一NMOS晶体管的栅极。 两个元件可能在对应于两个元件的相同温度稳定点的操作点处偏置。