公开(公告)号：US20190164973A1

公开(公告)日：2019-05-30

申请号：US16199810

申请日：2018-11-26

Applicant: STMicroelectronics SA

Inventor： Hassan EL DIRANI ,  Thomas BEDECARRATS ,  Philippe GALY

IPC: H01L27/108 ,  G11C11/402 ,  G11C11/409

Abstract: A memory array includes memory cells of Z2-FET type arranged in rows and columns, wherein each memory cell includes a MOS-type selection transistor and a first region of a first conductivity type that is shared in common with a drain region of the first conductivity type of the selection transistors. The selection transistors of a same column of the memory array have a common drain region, a common source region, and a common channel region.