公开(公告)号：US20200006320A1

公开(公告)日：2020-01-02

申请号：US16454230

申请日：2019-06-27

Applicant: STMicroelectronics SA

Inventor： Thomas BEDECARRATS ,  Louise DE CONTI ,  Philippe GALY

IPC: H01L27/02

Abstract: A semiconductor substrate includes a doped region having an upper surface. The doped region may comprise a conduction terminal of a diode (such as cathode) or a transistor (such as a drain). A silicide layer is provided at the doped region. The silicide layer has an area that only partially covers an area of the upper surface of the doped region. The partial area coverage facilitates modulating the threshold voltage and/or leakage current of an integrated circuit device.

公开(公告)号：US20230163117A1

公开(公告)日：2023-05-25

申请号：US18095728

申请日：2023-01-11

Applicant: STMicroelectronics SA

Inventor： Louise DE CONTI ,  Philippe GALY

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L27/0277 ,  H01L27/1203 ,  H01L29/7436

Abstract: An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.

公开(公告)号：US20190181131A1

公开(公告)日：2019-06-13

申请号：US16216541

申请日：2018-12-11

Applicant: STMicroelectronics SA

Inventor： Philippe GALY ,  Louise DE CONTI

IPC: H01L27/02 ,  H02H9/04

Abstract: An electronic device for providing ESD protection is formed by a MOS transistor. the MOS transistor includes a source region and a drain region that are separated from each other by a channel-forming region. A first gate is located over the channel forming region. The drain region includes an extension region. A second gate is located over the extension region. The first and second gates are electrically connected to each other.