公开(公告)号：US20130057334A1

公开(公告)日：2013-03-07

申请号：US13669259

申请日：2012-11-05

Applicant: STMicroelectronics SA ,  ST Ericsson SA

Inventor： Frederic Hasbani ,  Pascal Urard ,  Fabrice Blisson ,  David Jacquet

IPC: H03K3/00

CPC classification number: H03K19/0016 ,  H03K19/0013 ,  H03K2217/0018

Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.

Abstract translation: 本公开中描述的实施例涉及一种用于为集成系统提供电力的方法，包括以下动作：向系统提供电源，接地和体偏置电压，体偏置电压包括p沟道MOS晶体管的体偏置电压， 大于或低于电源电压，以及n沟道MOS晶体管的体偏置电压低于或大于接地电压，根据系统的处理单元是否由系统提供的电压进行选择 在活动或不活动的时段期间，提供用于偏置处理单元的MOS晶体管的主体的电压，以及为处理单元的MOS晶体管的主体提供所选择的电压。

公开(公告)号：US20140333360A1

公开(公告)日：2014-11-13

申请号：US14369118

申请日：2013-01-22

Applicant: ST-Ericsson SA

Inventor： David Jacquet ,  Philip O'Shea ,  Jacques Prunier

IPC: H03L7/00

CPC classification number: H03L7/00 ,  G06F1/12 ,  H03K5/135 ,  H04L7/0037

Abstract: The present invention relates to a signal synchronization circuit comprising at least one synchronizer (2.1-2.2) comprising a number N of series connected clock delay elements (3.1-3.3), N being equal to or greater than unity and a clock signal generator (1) arranged for generating a modulated clock signal adapted to clock the clock delay element (3.1-3.3) or elements of the at least one synchronizer (2.1-2.2). The clock generator (1) is arranged to receive a clock signal (5) and at least one operating value (6) and to generate the modulated clock signal (1 out) from the clock signal (5) modified based on the operating value (6).

Abstract translation: 信号同步电路技术领域本发明涉及一种信号同步电路，包括至少一个同步器（2.1-2.2），其包括N个串联连接的时钟延迟元件（3.1-3.3），N等于或大于1，以及时钟信号发生器 ），用于产生适于对所述时钟延迟元件（3.1-3.3）或所述至少一个同步器（2.1-2.2）的元件进行时钟的调制时钟信号。 时钟发生器（1）被布置成接收时钟信号（5）和至少一个操作值（6），并且从根据操作值（5）修改的时钟信号（5）产生调制时钟信号（1 out） 6）。

公开(公告)号：US09203415B2

公开(公告)日：2015-12-01

申请号：US14369118

申请日：2013-01-22

Applicant: ST-Ericsson SA

Inventor： David Jacquet ,  Philip O'Shea ,  Jacques Prunier

IPC: H03K5/135 ,  H03L7/00 ,  G06F1/12 ,  H04L7/00

CPC classification number: H03L7/00 ,  G06F1/12 ,  H03K5/135 ,  H04L7/0037

Abstract: The present invention relates to a signal synchronization circuit comprising at least one synchronizer (2.1-2.2) comprising a number N of series connected clock delay elements (3.1-3.3), N being equal to or greater than unity and a clock signal generator (1) arranged for generating a modulated clock signal adapted to clock the clock delay element (3.1-3.3) or elements of the at least one synchronizer (2.1-2.2). The clock generator (1) is arranged to receive a clock signal (5) and at least one operating value (6) and to generate the modulated clock signal (1 out) from the clock signal (5) modified based on the operating value (6).

Abstract translation: 信号同步电路技术领域本发明涉及一种信号同步电路，包括至少一个同步器（2.1-2.2），其包括N个串联连接的时钟延迟元件（3.1-3.3），N等于或大于1，以及时钟信号发生器 ），用于产生适于对所述时钟延迟元件（3.1-3.3）或所述至少一个同步器（2.1-2.2）的元件进行时钟的调制时钟信号。 时钟发生器（1）被布置成接收时钟信号（5）和至少一个操作值（6），并且从根据操作值（5）修改的时钟信号（5）产生调制时钟信号（1 out） 6）。