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公开(公告)号：US20250063661A1
公开(公告)日：2025-02-20
申请号：US18725200
申请日：2022-12-21
Inventor： Kenji TAKAHASHI , Shoichiro SAKAI , Satoshi KIYA
Abstract: A printed wiring board includes: a first conductive pattern; a dielectric layer that is disposed to cover the first conductive pattern; a second conductive pattern that is disposed on the dielectric layer; and a plating layer. A thickness of the dielectric layer is 50 μm or more and 500 μm or less. A hole from which the first conductive pattern is exposed is formed in the dielectric layer. An aspect ratio of the hole is 0.5 or more and 2.0 or less. The plating layer is disposed on at least an inner wall surface of the hole and the first conductive pattern exposed from the hole, and electrically connected to the second conductive pattern. A thickness of the plating layer disposed on the first conductive pattern exposed from the hole is greater than a thickness of the second conductive pattern.
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公开(公告)号：US20230232538A1
公开(公告)日：2023-07-20
申请号：US18010050
申请日：2021-06-25
Inventor： Toshiki IWASAKI , Makoto NAKABAYASHI , Satoshi KIYA
CPC classification number: H05K3/022 , H05K1/0366 , H05K1/036 , H05K2201/015
Abstract: A substrate for a printed wiring board includes a base layer, and a copper foil directly or indirectly stacked on at least a part of one or both surfaces of the base layer. The base layer includes a matrix containing a fluororesin as a main component and one or more reinforcing material layers included in the matrix, and a ratio B/A is 0.003 to 0.37, where A is an average thickness of the base layer, and B is an average distance between a surface of the copper foil facing the matrix and a surface of a reinforcing material layer closest to the surface of the copper foil facing the copper foil.
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公开(公告)号：US20220418094A1
公开(公告)日：2022-12-29
申请号：US17783094
申请日：2021-05-10
Inventor： Koji NITTA , Takafumi UEMIYA , Suguru YAMAGISHI , Shigeki SHIMADA , Hiroshi UEDA , Satoshi KIYA
IPC: H05K1/02
Abstract: A high-frequency circuit includes a first dielectric layer, a circuit layer, a second dielectric layer arranged in this order, the circuit layer includes a transmission line of a high-frequency signal and a ground pattern disposed around the transmission line. An electromagnetic wave shield is disposed in the first dielectric layer and the second dielectric layer around the transmission line. The electromagnetic wave shield includes a first ground electric conductor formed on an inner surface of at least one first hole formed to extend through the first dielectric layer without extending through the ground pattern, and a second ground electric conductor formed on an inner surface of at least one second hole formed to extend through the second dielectric layer without extending through the ground pattern. The first ground electric conductor and the second ground electric conductor are each electrically connected to the ground pattern.
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4.发明申请公开(公告)号：US20180242450A1
公开(公告)日：2018-08-23
申请号：US15753017
申请日：2016-08-06
Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD. , SUMITOMO ELECTRIC PRINTED CIRCUITS, INC. , SUMITOMO ELECTRIC FINE POLYMER, INC.
Inventor： Yuichiro YAMANAKA , Yoshio OKA , Satoshi KIYA , Yoshifumi UCHITA , Makoto NAKABAYASHI
IPC: H05K1/03 , H05K3/38 , B32B15/088
CPC classification number: H05K1/0346 , B32B15/08 , B32B15/088 , H05K3/381 , H05K3/389 , H05K2201/0154 , H05K2201/0355
Abstract: A substrate for a printed circuit board according to an embodiment of the present invention includes a base film and a metal layer disposed on at least one of surfaces of the base film. In the substrate for a printed circuit board, an amount of nitrogen present per unit area, the amount being determined on the basis of a peak area of a N1s spectrum in XPS analysis of a surface of the base film exposed after removal of the metal layer by etching with an acidic solution, is 1 atomic % or more and 10 atomic % or less.
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公开(公告)号：US20250159798A1
公开(公告)日：2025-05-15
申请号：US18839087
申请日：2023-02-22
Inventor： Satoshi KIYA , Kazuo MURATA , Hiroshi UEDA , Suguru YAMAGISHI , Ichiro KUWAYAMA , Yuichi NAKAMURA , Takanori FUKUNAGA
IPC: H05K1/02
Abstract: The printed wiring board includes a base film, a first conductor pattern, a protective layer, a conductive adhesive layer, and a conductor film. The base film has a first main surface. The first conductor pattern is disposed on the first main surface. The first conductor pattern includes a signal pattern, a first ground pattern, and a second ground pattern, each of which extends along a first direction in a planar view. The signal pattern is disposed between the first ground pattern and the second ground pattern in a second direction orthogonal to the first direction. The protective layer is disposed on the first main surface so as to cover the first conductor pattern.
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Patent Agency Ranking
公开(公告)号：US20190215957A1
公开(公告)日：2019-07-11
申请号：US16336211
申请日：2018-06-20
Inventor： Shingo KAIMORI , Masaaki YAMAUCHI , Kentaro OKAMOTO , Satoshi KIYA , Kazuo MURATA
Abstract: A first embodiment of a substrate for a high-frequency printed wiring board according to the present disclosure is directed to a substrate for a high-frequency printed wiring board, the substrate including: a dielectric layer including a fluororesin and an inorganic filler; and a copper foil layered on at least one surface of the dielectric layer, wherein a surface of the copper foil at the dielectric layer side has a maximum height roughness (Rz) of less than or equal to 2 μm, and a ratio of the number of inorganic atoms of the inorganic filler to the number of fluorine atoms of the fluororesin in a superficial region of the dielectric layer at the copper foil side is less than or equal to 0.08.
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公开(公告)号：US20250071892A1
公开(公告)日：2025-02-27
申请号：US18725177
申请日：2022-12-21
Inventor： Kenji TAKAHASHI , Shoichiro SAKAI , Satoshi KIYA
IPC: H05K1/02
Abstract: A printed wiring board includes: a base material having a main surface; a conductive pattern that is disposed on the main surface; and a plating layer. A through hole is formed in the base material. The through hole extends through the base material in a thickness direction. A thickness of the base material is 0.5 mm or more. The plating layer is disposed on at least an inner wall surface of the through hole and electrically connected to a portion of the conductive pattern around the through hole. A thickness of the plating layer on the inner wall surface of the through hole is greater than a thickness of the conductive pattern and 10 μm or more.
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公开(公告)号：US20250063651A1
公开(公告)日：2025-02-20
申请号：US18725297
申请日：2022-12-21
Inventor： Kazuhiro MIYATA , Koji NITTA , Shoichiro SAKAI , Satoshi KIYA
Abstract: A printed wiring board includes: a dielectric layer having a main surface; and a conductive pattern. The conductive pattern includes a metal layer that is disposed on the main surface, an electroless plating layer that is disposed on the metal layer, and an electrolytic plating layer that is disposed on the electroless plating layer. An average thickness of the metal layer is 2.1 μm or more and 9.0 μm or less. Maximum height roughness of a surface of the metal layer opposed to the main surface is 5.0 μm or less.
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公开(公告)号：US20230019563A1
公开(公告)日：2023-01-19
申请号：US17783138
申请日：2021-05-10
Inventor： Koji NITTA , Takafumi UEMIYA , Suguru YAMAGISHI , Shigeki SHIMADA , Hiroshi UEDA , Satoshi KIYA
Abstract: A high-frequency circuit includes a first electric conductor layer, a first dielectric layer, a circuit layer, a second dielectric layer, a second electric conductor layer arranged in this order, and the circuit layer includes a ground pattern and a transmission line of a high-frequency signal. An electromagnetic wave shield is disposed around the transmission line. The electromagnetic wave shield includes a ground electric conductor on inner surfaces of a plurality of holes extending through the first dielectric layer, the ground pattern, the second dielectric layer, the first electric conductor layer, and the second electric conductor layer. The plurality of holes are a plurality of elongated holes provided at an interval in a direction in which the transmission line is surrounded. In each of the plurality of elongated holes, a longitudinal dimension in the direction in which the transmission line is surrounded is larger than a width dimension.
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公开(公告)号：US20220272838A1
公开(公告)日：2022-08-25
申请号：US17632016
申请日：2021-05-11
Inventor： Shingo KAIMORI , Takashi NINOMIYA , Motohiko SUGIURA , Yasuhiro OKUDA , Hideki KASHIHARA , Satoshi KIYA , Makoto NAKABAYASHI , Kentaro OKAMOTO , Chiaki TOKUDA
Abstract: A method for manufacturing a dielectric sheet, includes the steps of extrusion molding a mixture including powder polytetrafluoroethylene and spherical silica at a temperature lower than or equal to a melting point of the polytetrafluoroethylene, and calendering a sheet body obtained by the extrusion molding. A mass ratio of the silica with respect to the polytetrafluoroethylene is 1.3 or greater. An average particle diameter of the silica is 0.1 μm or greater but 3.0 μm or less. A reduction ratio of the extrusion molding is 8 or less.
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