公开(公告)号：US20170047342A1

公开(公告)日：2017-02-16

申请号：US15173888

申请日：2016-06-06

申请人： SUNG MIN HWANG ,  Jang Gn Yun ,  Ahn Sik Moon ,  Se Jun Park ,  Zhiliang Xia ,  Joon Sung Lim

发明人： SUNG MIN HWANG ,  Jang Gn Yun ,  Ahn Sik Moon ,  Se Jun Park ,  Zhiliang Xia ,  Joon Sung Lim

IPC分类号： H01L27/115 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

摘要： A semiconductor device includes a gate stack including gate electrodes stacked vertically on a substrate. Channel holes penetrate through the gate stack to extend vertically to the substrate. Each of the channel holes includes a channel region. First channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the first channel pads includes at least one first conductivity-type impurity. Second channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the second channel pads includes at least one second conductivity-type impurity.

摘要翻译： 半导体器件包括栅极堆叠，其包括垂直堆叠在衬底上的栅电极。 通道孔穿过栅极堆叠，以垂直于衬底延伸。 每个通道孔包括通道区域。 第一通道焊盘各自设置在与衬底相对的相应通道孔的端部。 每个第一通道焊盘包括至少一种第一导电型杂质。 第二通道焊盘各自设置在与衬底相对的相应通道孔的端部。 每个第二通道焊盘包括至少一个第二导电类型的杂质。