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公开(公告)号：US10409943B2
公开(公告)日：2019-09-10
申请号：US14475276
申请日：2014-09-02
Applicant: SYNOPSYS, INC.
Inventor： Tung-Chieh Chen , Po-Cheng Pan , Ching-Yu Chin , Hung-Ming Chen
IPC: G06F17/50
Abstract: A computer implemented method for routing preservation is presented. The method includes decomposing, using the computer, a geometric relationship between a first module, a second module, and a routing path of a source layout, when the computer is invoked to route the solution path. The method further includes disposing, using the computer, the routing path in a solution layout in accordance with the geometric relationship. The solution layout is not defined by a scaling of the source layout.
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公开(公告)号：US09286433B2
公开(公告)日：2016-03-15
申请号：US14082885
申请日：2013-11-18
Applicant: Synopsys Taiwan Co. Ltd. , Synopsys, Inc.
Inventor： Tung-Chieh Chen , Hung-Ming Chen , Yi-Peng Weng
CPC classification number: G06F17/5081 , G06F17/5072 , G06F2217/06
Abstract: A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.
Abstract translation: 提出了一种用于形成集成电路（IC）布局的计算机实现方法。 该方法包括当调用计算机以接收IC的第一布局并根据约束树生成IC的第二布局时，形成约束树。
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公开(公告)号：US20140075402A1
公开(公告)日：2014-03-13
申请号：US14082885
申请日：2013-11-18
Applicant: Synopsys, Inc. , Synopsys Taiwan Co. Ltd.
Inventor： Tung-Chieh Chen , Hung-Ming Chen , Yi-Peng Weng
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5072 , G06F2217/06
Abstract: A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.
Abstract translation: 提出了一种用于形成集成电路（IC）布局的计算机实现方法。 该方法包括当调用计算机以接收IC的第一布局并根据约束树生成IC的第二布局时，形成约束树。
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