公开(公告)号：US5587686A

公开(公告)日：1996-12-24

申请号：US300284

申请日：1994-09-02

申请人： Salil Suri ,  Sassan Teymouri

发明人： Salil Suri ,  Sassan Teymouri

IPC分类号： G06F13/40 ,  H03K5/1252 ,  H03K5/00 ,  H03K9/06

CPC分类号： G06F13/4072 ,  H03K5/1252

摘要： A time domain signal filter detects a change in an input signal and replaces the input signal with an internally generated substitute signal for a filter period. The filter period is user selectable and can be set through a bit in a hardware register. After passage of the filter period, the time domain signal filter resumes direct supply of the input signal as the output signal. The time domain signal filter determines the start of the filter period by using either the falling edge or the rising edge of the clock input, whichever edge comes first after detecting the change in the input signal.

摘要翻译： 时域信号滤波器检测输入信号的变化，并用滤波器周期的内部产生的替代信号替换输入信号。 滤波器周期是用户可选择的，可以通过硬件寄存器中的位进行设置。 滤波器周期过后，时域信号滤波器恢复直接输入输入信号作为输出信号。 时域信号滤波器通过使用时钟输入的下降沿或上升沿来确定滤波器周期的开始，无论哪个边缘在检测到输入信号的变化之后都先到。

公开(公告)号：US5113098A

公开(公告)日：1992-05-12

申请号：US677550

申请日：1991-03-29

申请人： Sassan Teymouri

发明人： Sassan Teymouri

IPC分类号： H03K3/3565 ,  H03K5/1252

CPC分类号： H03K3/3565 ,  H03K5/1252

摘要： Glitch remover circuit for removing glitches and spikes from control signals received on a SCSI bus line that is coupled from a transmission line includes an input buffer circuit (12) and a filter circuit (14). The input buffer circuit is of a Schmitt trigger type having a transfer characteristic with hysteresis. The input buffer circuit (12) is responsive to control signals received at its input for removing noise spikes around the threshold point of its input on both the rising and falling edges of the control signals so as to provide a pulsed output voltage. The filter circuit (14) is responsive to the pulsed output voltage for generating a filtered pulsed signal at an output terminal only when the pulsed output voltage has a pulse width which is longer than a predetermined time. The filter circuit includes a delay means (28), a gating means (30) and inverter means (32).

摘要翻译： 用于从传输线耦合的SCSI总线上接收的控制信号去除毛刺和峰值的毛刺去除器电路包括输入缓冲电路（12）和滤波电路（14）。 输入缓冲电路是具有滞后传输特性的施密特触发型。 输入缓冲器电路（12）响应于在其输入处接收的控制信号，以在控制信号的上升沿和下降沿上除去其输入的阈值点附近的噪声尖峰，从而提供脉冲输出电压。 滤波器电路（14）响应于脉冲输出电压，用于仅在脉冲输出电压具有比预定时间长的脉冲宽度时在输出端产生经滤波的脉冲信号。 滤波器电路包括延迟装置（28），门控装置（30）和反相装置（32）。