公开(公告)号：US5587686A

公开(公告)日：1996-12-24

申请号：US300284

申请日：1994-09-02

申请人： Salil Suri ,  Sassan Teymouri

发明人： Salil Suri ,  Sassan Teymouri

IPC分类号： G06F13/40 ,  H03K5/1252 ,  H03K5/00 ,  H03K9/06

CPC分类号： G06F13/4072 ,  H03K5/1252

摘要： A time domain signal filter detects a change in an input signal and replaces the input signal with an internally generated substitute signal for a filter period. The filter period is user selectable and can be set through a bit in a hardware register. After passage of the filter period, the time domain signal filter resumes direct supply of the input signal as the output signal. The time domain signal filter determines the start of the filter period by using either the falling edge or the rising edge of the clock input, whichever edge comes first after detecting the change in the input signal.

摘要翻译： 时域信号滤波器检测输入信号的变化，并用滤波器周期的内部产生的替代信号替换输入信号。 滤波器周期是用户可选择的，可以通过硬件寄存器中的位进行设置。 滤波器周期过后，时域信号滤波器恢复直接输入输入信号作为输出信号。 时域信号滤波器通过使用时钟输入的下降沿或上升沿来确定滤波器周期的开始，无论哪个边缘在检测到输入信号的变化之后都先到。

公开(公告)号：US07382788B2

公开(公告)日：2008-06-03

申请号：US10435214

申请日：2003-05-08

申请人： Scott Furey ,  Salil Suri ,  Michael Moretti ,  Thomas Wu ,  David Geddes

发明人： Scott Furey ,  Salil Suri ,  Michael Moretti ,  Thomas Wu ,  David Geddes

IPC分类号： H04L12/28

CPC分类号： H04L69/22

摘要： A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

摘要翻译： 公开了一种桥接网络协议的方法和装置。 在一个实施例中，数据帧被硬件逻辑接收并存储在双端口存储器队列中。 一旦数据帧的可编程数量的字节已经被接收和存储，嵌入式处理器就被通知数据帧。 一旦通知，当硬件逻辑仍在写入存储器队列时，嵌入式处理器然后可以承担从存储器队列读取数据帧。 在一个实施例中，处理器然后可以转换数据帧的协议，并且开始通过网络连接发送它，同时数据帧的有效载荷仍在被接收。

公开(公告)号：US08170035B2

公开(公告)日：2012-05-01

申请号：US12106125

申请日：2008-04-18

申请人： Scott Furey ,  Salil Suri ,  Michael Moretti ,  Thomas Wu ,  David Geddes

发明人： Scott Furey ,  Salil Suri ,  Michael Moretti ,  Thomas Wu ,  David Geddes

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04J3/16 ,  H04J3/22

CPC分类号： H04L69/22

摘要： A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

摘要翻译： 公开了一种桥接网络协议的方法和装置。 在一个实施例中，数据帧被硬件逻辑接收并存储在双端口存储器队列中。 一旦数据帧的可编程数量的字节已经被接收和存储，嵌入式处理器就被通知数据帧。 一旦通知，当硬件逻辑仍在写入存储器队列时，嵌入式处理器然后可以承担从存储器队列读取数据帧。 在一个实施例中，处理器然后可以转换数据帧的协议，并且开始通过网络连接发送它，同时数据帧的有效载荷仍在被接收。

公开(公告)号：US06298403B1

公开(公告)日：2001-10-02

申请号：US09089030

申请日：1998-06-02

申请人： Salil Suri ,  Taikhim Henry Tan

发明人： Salil Suri ,  Taikhim Henry Tan

IPC分类号： G06F1300

CPC分类号： G06F13/387

摘要： A circuit collects data from a number of locations in a system memory of a personal computer, and can refetch the collected data at any time, e.g. when an adapter for transferring data between a computer bus and a peripheral bus that includes the circuit encounter an unexpected event (such as an error) in the transmission (or retransmission) of data to a first peripheral device. So the adapter simply flushes the data on encountering the unexpected event. Thereafter, the adapter switches context, to transfer data to a second peripheral device. At a later time, the circuit in the adapter refetches the flushed data, for retransmission of the data to the first peripheral device. To refetch the flushed data, the circuit does not traverse backwards through a scatter/gather data transfer pointer list (described above) that is used to collect the data from system memory. Instead, the circuit initially stores the values (collectively called “snapshot”) of signals in various registers at the time of initial receipt of the data, and at a later time loads the saved snapshot to refetch data that was flushed.

摘要翻译： 电路从个人计算机的系统存储器中的多个位置收集数据，并且可以随时重新获取所收集的数据，例如， 当用于在计算机总线和包括该电路的外围总线之间传送数据的适配器在向第一外围设备发送（或重传）数据时遇到意外事件（例如错误）。 因此，适配器只是在遇到意外事件时刷新数据。 此后，适配器切换上下文以将数据传送到第二外围设备。 稍后，适配器中的电路重新获取刷新的数据，用于将数据重新发送到第一外围设备。 为了获取刷新的数据，电路不会向后穿过用于从系统存储器收集数据的分散/收集数据传输指针列表（如上所述）。 相反，电路在初始接收数据时最初将信号的值（统称为“快照”）存储在各种寄存器中，并且稍后加载保存的快照以重新获取被刷新的数据。

公开(公告)号：US6070200A

公开(公告)日：2000-05-30

申请号：US89311

申请日：1998-06-02

申请人： Stillman F. Gates ,  Salil Suri

发明人： Stillman F. Gates ,  Salil Suri

IPC分类号： G06F13/12 ,  G06F13/00

CPC分类号： G06F13/122

摘要： A host adapter has receive and transmit data paths, each of which includes a buffer (formed of storage elements) for temporarily holding the data being transferred by the host adapter. The host adapter uses each of the two buffers for storing only the data being transferred in the respective direction, each independent of the other, for full-duplex data transfer therethrough. To permit parallel flow-through operation, each of the two buffers is organized into a number of fixed-sized pages that are accessible via the peripheral bus only one page at a time. To maximize bandwidth and minimize latency, during operation in any given direction of data transfer (e.g. from the computer bus to the peripheral bus or vice versa) the host adapter uses at least two pages in a data path simultaneously: one for receipt and another for transmission. Specifically, each data path uses one page to hold data that is currently being received, while using another page containing data that was previously received for simultaneous transmission from the host adapter. Each of the data paths transfers data in a continuous manner irrespective of the context (e.g. peripheral device address, or system memory address or a sequence identifier of a Fibre Channel frame) of the data. Specifically, each data path uses one page to hold data that is currently being received from one context, while using another page containing data of another context that was previously received for simultaneous transmission from the host adapter.

摘要翻译： 主机适配器具有接收和发送数据路径，每个数据路径包括用于临时保存由主机适配器传送的数据的缓冲器（由存储元件形成）。 主机适配器使用两个缓冲器中的每一个仅存储在相应方向上传送的数据，每个缓冲器独立于另一个，用于通过其进行全双工数据传输。 为了允许并行流通操作，两个缓冲器中的每一个被组织成多个固定大小的页面，其可以通过外围总线一次访问一页。 为了最大化带宽和最小化延迟，在任何给定方向的数据传输（例如从计算机总线到外围总线或反之亦然）的操作期间，主机适配器在数据通路中同时使用至少两个页面：一个用于接收，另一个用于 传输。 具体来说，每个数据路径使用一个页面来保存当前正在接收的数据，同时使用另一个页面，该页面包含先前接收的用于从主机适配器同时发送的数据。 每个数据路径以连续的方式传送数据，而不管数据的上下文（例如外围设备地址，或系统存储器地址或光纤通道帧的序列标识符）。 特别地，每个数据路径使用一页来保存当前正在从一个上下文接收的数据，同时使用另一个页面，该页面包含先前接收的用于从主机适配器同时发送的另一上下文的数据。

公开(公告)号：US07260112B2

公开(公告)日：2007-08-21

申请号：US10659538

申请日：2003-09-09

申请人： Michael Moretti ,  David Geddes ,  Thomas Wu ,  Salil Suri ,  Scott Furey

发明人： Michael Moretti ,  David Geddes ,  Thomas Wu ,  Salil Suri ,  Scott Furey

IPC分类号： H04J3/16 ,  H04J3/22

CPC分类号： H04J3/1617 ,  H04J2203/0067 ,  H04J2203/0082 ,  H04L29/06 ,  H04L69/08

摘要： Methods and apparatus for bridging network protocols are disclosed. A protocol bridge may be used to function as a target for a network processor while performing a target mode operation, while functioning as an initiator on behalf of the network processor while performing an initiator mode operation. In one embodiment, the protocol bridge determines the mode of operation based on information in a received frame's header. In another embodiment, the protocol bridge couples a Fiber Channel device to a storage processor on a packet-over-SONET network.

摘要翻译： 公开了桥接网络协议的方法和装置。 当执行目标模式操作时，可以使用协议桥作为网络处理器的目标，同时在执行启动器模式操作时用作代表网络处理器的启动器。 在一个实施例中，协议桥基于接收帧的头部中的信息来确定操作模式。 在另一实施例中，协议桥将光纤通道设备耦合到SONET网络上的存储处理器。

公开(公告)号：US07239645B2

公开(公告)日：2007-07-03

申请号：US10659535

申请日：2003-09-09

申请人： Salil Suri ,  David Geddes ,  Scott Furey ,  Michael Moretti ,  Thomas Wu

发明人： Salil Suri ,  David Geddes ,  Scott Furey ,  Michael Moretti ,  Thomas Wu

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L49/9021 ,  G06F5/10 ,  H04J3/1617 ,  H04J2203/0082 ,  H04J2203/0089 ,  H04L47/50 ,  H04L47/624 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047

摘要： A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

摘要翻译： 公开了一种桥接网络协议的方法和装置。 在一个实施例中，数据帧被硬件逻辑接收并存储在双端口存储器队列中。 一旦数据帧的可编程数量的字节已经被接收和存储，嵌入式处理器就被通知数据帧。 一旦通知，当硬件逻辑仍在写入存储器队列时，嵌入式处理器然后可以承担从存储器队列读取数据帧。 在一个实施例中，处理器然后可以转换数据帧的协议，并且开始通过网络连接发送它，同时数据帧的有效载荷仍在被接收。

公开(公告)号：US07962647B2

公开(公告)日：2011-06-14

申请号：US12276676

申请日：2008-11-24

申请人： Salil Suri ,  Harish Chilkoti

发明人： Salil Suri ,  Harish Chilkoti

IPC分类号： G06F13/00

CPC分类号： H04L45/22 ,  H04L45/00 ,  H04L45/125 ,  H04L47/125

摘要： A virtualized platform includes a virtual switch connected to the virtual network interface cards (vNICs) for a group of virtual machines running the same application program that is associated with multiple software ports. A module in the virtualized platform monitors the virtual switch's receipt of a network packet that includes control information relating to the application program and its software ports. The module applies a load balancing algorithm to select a vNIC from the vNICs connected or connectable to the virtual switch, based on the rate of processing of previous network packets by each the vNICs (e.g., as measured by the size of a network packet queue). The module might also apply the load balancing algorithm to select a software port for the application. The module then causes the virtual switch to route the network packet to the selected vNIC and software port.

摘要翻译： 虚拟化平台包括连接到虚拟网络接口卡（vNIC）的虚拟交换机，用于运行与多个软件端口相关联的相同应用程序的一组虚拟机。 虚拟化平台中的一个模块监视虚拟交换机对包含与应用程序及其软件端口相关的控制信息的网络数据包的接收。 该模块基于每个vNIC对先前网络分组的处理速率（例如，按网络分组队列的大小测量），应用负载平衡算法从连接或可连接到虚拟交换机的vNIC中选择一个vNIC， 。 该模块还可以应用负载平衡算法为应用程序选择一个软件端口。 该模块然后使虚拟交换机将网络数据包路由到所选的vNIC和软件端口。

公开(公告)号：US20080205441A1

公开(公告)日：2008-08-28

申请号：US12106125

申请日：2008-04-18

申请人： Scott Furey ,  Salil Suri ,  Michael Moretti ,  Thomas Wu ,  David Geddes

发明人： Scott Furey ,  Salil Suri ,  Michael Moretti ,  Thomas Wu ,  David Geddes

IPC分类号： H04L29/08

CPC分类号： H04L69/22

摘要： A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

摘要翻译： 公开了一种桥接网络协议的方法和装置。 在一个实施例中，数据帧被硬件逻辑接收并存储在双端口存储器队列中。 一旦数据帧的可编程数量的字节已经被接收和存储，嵌入式处理器就被通知数据帧。 一旦通知，当硬件逻辑仍在写入存储器队列时，嵌入式处理器然后可以承担从存储器队列读取数据帧。 在一个实施例中，处理器然后可以转换数据帧的协议，并且开始通过网络连接发送它，同时数据帧的有效载荷仍在被接收。

公开(公告)号：US20070268929A1

公开(公告)日：2007-11-22

申请号：US11821073

申请日：2007-06-21

申请人： Michael Moretti ,  David Geddes ,  Thomas Wu ,  Salil Suri ,  Scott Furey

发明人： Michael Moretti ,  David Geddes ,  Thomas Wu ,  Salil Suri ,  Scott Furey

IPC分类号： H04L12/66 ,  H04J3/16 ,  H04J3/22

CPC分类号： H04J3/1617 ,  H04J2203/0067 ,  H04J2203/0082 ,  H04L29/06 ,  H04L69/08

摘要： Methods and apparatus for bridging network protocols are disclosed. A protocol bridge may be used to function as a target for a network processor while performing a target mode operation, while functioning as an initiator on behalf of the network processor while performing an initiator mode operation. In one embodiment, the protocol bridge determines the mode of operation based on information in a received frame's header. In another embodiment, the protocol bridge couples a Fibre Channel device to a storage processor on a packet-over-SONET network.

摘要翻译： 公开了桥接网络协议的方法和装置。 当执行目标模式操作时，可以使用协议桥作为网络处理器的目标，同时在执行启动器模式操作时用作代表网络处理器的启动器。 在一个实施例中，协议桥基于接收帧的头部中的信息来确定操作模式。 在另一实施例中，协议桥将光纤通道设备耦合到SONET网络上的存储处理器。