公开(公告)号：US20050289253A1

公开(公告)日：2005-12-29

申请号：US10877587

申请日：2004-06-24

申请人： Samantha Edirisooriya ,  Joseph Murray ,  Gregory Tse ,  Vishram Sarurkar ,  Manish Goel

发明人： Samantha Edirisooriya ,  Joseph Murray ,  Gregory Tse ,  Vishram Sarurkar ,  Manish Goel

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A method and apparatus for a multi-function direct memory access core are described. In one embodiment, the method includes the reading of a direct memory access (DMA) descriptor having associated DMA data to identify at least one micro-command. Once the micro-command is identified, the DMA data is processed according to the micro-command during DMA transfer of the data. In one embodiment, a DMA engine performs an operation on the DMA data in transit within the DMA controller according to the identified micro-command. Hence, by defining a primitive set of micro-commands, the DMA engine within, for example, an input/output (I/O) controller hub (ICH), can be used to perform a large number of complex operations on data when data is passing through the ICH without introducing latency into the DMA transfer. Other embodiments are described and claimed.

摘要翻译： 描述了用于多功能直接存储器存取核心的方法和装置。 在一个实施例中，该方法包括读取具有相关DMA数据的直接存储器访问（DMA）描述符，以识别至少一个微指令。 一旦识别了微型命令，在DMA传输数据期间，根据微指令对DMA数据进行处理。 在一个实施例中，DMA引擎根据所识别的微指令对DMA控制器内的DMA数据执行操作。 因此，通过定义基本的微指令集，例如在输入/输出（I / O）控制器集线器（ICH）内的DMA引擎可用于对数据执行大量的复杂操作 正在通过ICH，而不会在DMA传输中引入延迟。 描述和要求保护其他实施例。

公开(公告)号：US20060136619A1

公开(公告)日：2006-06-22

申请号：US11017183

申请日：2004-12-16

申请人： Samantha Edirisooriya ,  Gregory Tse ,  Joseph Murray

发明人： Samantha Edirisooriya ,  Gregory Tse ,  Joseph Murray

IPC分类号： G06F5/00

CPC分类号： G06F13/28

摘要： Techniques to accelerate block guard processing of data by use of block guard units in a path between a source memory device and an originator of a data transfer request. The block guard unit may intercept the data transfer request and data transferred in response to the data transfer request. The block guard unit may utilize a cache to store information useful to verify block guards associated with the data.

摘要翻译： 通过使用源存储器设备和数据传输请求的发起者之间的路径中的块保护单元来加速对数据的块保护处理的技术。 块保护单元可以拦截响应于数据传输请求传送的数据传输请求和数据。 块保护单元可以利用高速缓存来存储用于验证与数据相关联的块保护的有用信息。

公开(公告)号：US20060143358A1

公开(公告)日：2006-06-29

申请号：US11027709

申请日：2004-12-28

申请人： Samantha Edirisooriya ,  Steven Tu ,  Gregory Tse ,  Sujat Jamil ,  David Miner ,  R. O'Bleness ,  Hang Nguyen

发明人： Samantha Edirisooriya ,  Steven Tu ,  Gregory Tse ,  Sujat Jamil ,  David Miner ,  R. O'Bleness ,  Hang Nguyen

IPC分类号： G06F13/00

CPC分类号： G06F13/36 ,  G06F13/4022

摘要： Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.

公开(公告)号：US20060156211A1

公开(公告)日：2006-07-13

申请号：US11021708

申请日：2004-12-23

申请人： Samantha Edirisooriya ,  Gregory Tse ,  Mark Schmisseur ,  Robert Sheffield

发明人： Samantha Edirisooriya ,  Gregory Tse ,  Mark Schmisseur ,  Robert Sheffield

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： G06F11/1076 ,  G06F2211/1004 ,  G06F2211/1057

摘要： A method and system for syndrome generation and data recovery is described. The system includes a recovery device coupled to one or more storage devices to recover data in the storage devices. The recovery device includes a first comparator to generate a first parity factor based on data in one or more of the storage devices, a multiplier to multiply data from one or more of the storage devices with a multiplication factor to generate a product, and a second comparator coupled to the multiplier to generate a second parity factor based at least in part on the product.

摘要翻译： 描述了一种用于综合征生成和数据恢复的方法和系统。 该系统包括耦合到一个或多个存储设备以恢复存储设备中的数据的恢复设备。 恢复装置包括：第一比较器，用于基于存储装置中的一个或多个中的数据产生第一奇偶校验因子;乘法器，用于将来自一个或多个存储装置的数据与乘法因子相乘以产生乘积;以及第二比较器 比较器耦合到乘法器，以至少部分地基于产品来产生第二奇偶校验因子。

公开(公告)号：US20070079032A1

公开(公告)日：2007-04-05

申请号：US11241161

申请日：2005-09-30

申请人： Sailesh Bissessur ,  Joseph Murray ,  Brian Skerry ,  Robert Sheffield ,  Richard Beckett ,  Gregory Tse

发明人： Sailesh Bissessur ,  Joseph Murray ,  Brian Skerry ,  Robert Sheffield ,  Richard Beckett ,  Gregory Tse

IPC分类号： G06F13/38

CPC分类号： G06F13/4291

摘要： An apparatus may include a Serial General Purpose Input Output (SGPIO) initiator device. The SGPIO initiator device may have terminals to receive parallel input signals. The device may also have parallel-to-serial conversion logic to convert the parallel input signals to a serial stream. The device may further have signal ordering logic. The signal ordering logic may be in communication with the terminals and may be in communication with the parallel-to-serial conversion logic. The signal ordering logic may determine an order in which the parallel input signals are provided in the serial stream. Methods of ordering signals within an SGPIO initiator device and systems having SGPIO initiator devices are also disclosed.

摘要翻译： 设备可以包括串行通用输入输出（SGPIO）启动器设备。 SGPIO启动器设备可以具有用于接收并行输入信号的终端。 该器件还可具有并行到串行转换逻辑，以将并行输入信号转换为串行流。 该装置还可以具有信号排序逻辑。 信号排序逻辑可以与终端通信，并且可以与并行到串行转换逻辑通信。 信号排序逻辑可以确定在串行流中提供并行输入信号的顺序。 还公开了在SGPIO启动器设备和具有SGPIO启动器设备的系统中排序信号的方法。