公开(公告)号：US20240020265A1

公开(公告)日：2024-01-18

申请号：US18221685

申请日：2023-07-13

Applicant: SambaNova Systems, Inc.

Inventor： Yue FU ,  Kin Hing LEUNG ,  Likun HAO ,  Arvind Krishna SUJEETH ,  Sumti JAIRATH ,  Andrew DENG ,  Chris RÉ ,  Raghu PRABHAKAR

IPC: G06F15/78

CPC classification number: G06F15/7871

Abstract: A system with a cost estimation tool for estimating a realized bandwidth consumption of a logical edge between a logical producer unit and a logical consumer unit of an operation unit graph during placement and routing of the logical producer unit, the logical consumer unit, and the logical edge onto a reconfigurable processor is presented as well as a method of operating such a cost estimation tool and a non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate such a cost estimation tool The cost estimation tool may be configured to determine the realized bandwidth consumption of the tentative assignment based on an upper bandwidth limit of the logical edge, an end-to-end bandwidth, a scaling factor of a realized bandwidth, and a congestion estimation of the physical link.

公开(公告)号：US20230315802A1

公开(公告)日：2023-10-05

申请号：US18128076

申请日：2023-03-29

Applicant: SambaNova Systems, Inc.

Inventor： Junjue WANG ,  Blaine Burton RISTER ,  Zhichao MA ,  Zhuo CHEN ,  Andrew DENG ,  Sumti JAIRATH ,  Arvind Krishna SUJEETH

IPC: G06F17/11

CPC classification number: G06F17/11

Abstract: A method comprises a compiler generating a MI (mixed integer) model to determine mapping decisions to map a dataflow application to hardware of a computing system to execute the application. The MI model comprises MI equations to solve by an MI solver. The MI equations include equations of an objective function corresponding to an optimization objective. The MI equations can comprise decision variables and equations and constraint variables and equations. The compiler outputs the MI model to the MI solver and invokes the MI solver to compute an MI solution comprising solutions to equations among the equations included in the MI model. The compiler receives the MI solution and generates a globally optimized mapping decision based on the MI solution. The MI solver can comprise a commercial program to solve MI linear equations. A computer program product and a computing system can implement the method.

公开(公告)号：US20240020170A1

公开(公告)日：2024-01-18

申请号：US18221678

申请日：2023-07-13

Applicant: SambaNova Systems, Inc.

Inventor： Yue FU ,  Kin Hing LEUNG ,  Arvind Krishna SUJEETH ,  Sumti JAIRATH ,  Andrew DENG ,  Chris RÉ ,  Raghu PRABHAKAR

IPC: G06F9/50 ,  G06F13/40

CPC classification number: G06F9/5044 ,  G06F13/4063

Abstract: A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for estimating a cost of implementing an operation unit graph. The operation unit graph may include first and second logical units that perform first and second data operations and have first and second ports, respectively, coupled by a logical edge, on a reconfigurable processor. The method includes receiving the operation unit graph, determining first and second upper bandwidth limits of the first and second ports, respectively, determining a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits, determining a timing group for the logical edge, and providing the logical edge bandwidth and the timing group as a cost estimation of implementing the operation unit graph on the reconfigurable processor.

公开(公告)号：US20230162032A1

公开(公告)日：2023-05-25

申请号：US17990556

申请日：2022-11-18

Applicant: SambaNova Systems, Inc.

Inventor： Etash Kumar GUHA ,  Tianxiao JIANG ,  Andrew DENG ,  Jian ZHANG ,  Muthiah ANNAMALAI

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: A method for estimating throughput for placement graphs includes obtaining a set of reference placement graphs for at least one computing task, determining a corresponding throughput value for each reference placement graph, configuring a graph neural network for each reference placement graph and training the graph neural network using each corresponding throughput value as a training target to produce a trained graph neural network. The method further includes configuring the trained graph neural network for a candidate placement graph corresponding to a target computing task, and using the trained graph neural network to estimate a throughput for the target computing task when conducted on a reconfigurable dataflow computing system using the candidate placement graph. The method may also include generating configuration information, configuring the reconfigurable dataflow computing system, and conducting the target computing task. A corresponding system and computer-readable medium are also disclosed herein.

公开(公告)号：US20240086235A1

公开(公告)日：2024-03-14

申请号：US18367764

申请日：2023-09-13

Applicant: SambaNova Systems, Inc.

Inventor： Tianxiao JIANG ,  Jian ZHANG ,  Etash Kumar GUHA ,  Andrew DENG ,  Muthiah ANNAMALAI

IPC: G06F9/48 ,  G06F9/30

CPC classification number: G06F9/4881 ,  G06F9/3005

Abstract: Reconfigurable dataflow architecture is an emerging design for deep learning training accelerator. This architecture maps model operators to an accelerator in a spatial way, enabling pipeline parallelization for high throughput. An essential ingredient to exploit this throughput advantage is compiler Performance Optimization (PO) which searches for optimal model mappings. The convention in industry-leading dataflow compilation uses hand-tuned rules to guide PO, requiring immense engineering cost to develop. This paper challenges this convention and asks if data-driven learned performance optimization can reduce the engineering cost while improving training throughput over hand-tuned rules. We present a workflow which guides PO using simple machine learning models trained from throughput observations of randomly generated mappings. We empirically show that developing and integrating these learned models into an industrial compiler can be 10× more efficient than hand-tuned rules in terms of engineering time cost.

公开(公告)号：US20240020264A1

公开(公告)日：2024-01-18

申请号：US18221683

申请日：2023-07-13

Applicant: SambaNova Systems, Inc.

Inventor： Yue FU ,  Kin Hing LEUNG ,  Joshua BROT ,  Arvind Krishna SUJEETH ,  Sumti JAIRATH ,  Andrew DENG ,  Chris RÉ ,  Raghu PRABHAKAR

IPC: G06F15/78

CPC classification number: G06F15/7871

Abstract: A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for determining scaled logical edge bandwidths in an operation unit graph in preparation of placing and routing the operation unit graph onto a reconfigurable processor. The cost estimation tool may be configured to receive the operation unit graph, divide the operation unit graph in first and second subgraphs, determine maximum latencies of the first and second subgraphs, and determine a scaled logical edge bandwidth of a logical edge that couples a first logical unit of M logical units in the first subgraph with a second logical unit of N logical units in the first subgraph based on M, N, and scaled bandwidth limits of the M and N logical units.