公开(公告)号：US20230315407A1

公开(公告)日：2023-10-05

申请号：US18129722

申请日：2023-03-31

Applicant: SambaNova Systems, Inc.

Inventor： Bowen YANG ,  Zhuo CHEN ,  Fei WANG ,  Venkat Krishna SRINIVASAN ,  Chen LIU ,  Junjue WANG ,  Arvind Krishna SUJEETH ,  Sumti JAIRATH

IPC: G06F8/41

CPC classification number: G06F8/433

Abstract: According to a computing method a compiler determines a recompute node included in a dataflow application and a checkpoint tensor produced by the recompute node. The compiler determines a recompute cost to recompute the checkpoint tensor, and a memory cost to checkpoint the checkpoint tensor in a memory. Based on the recompute cost and/or the memory cost, the compiler determines a solution cost and compares the solution cost to a solution threshold. Based on comparing the solution cost to the solution threshold, the compiler determines a checkpoint solution to execute the dataflow application. The checkpoint solution can comprise recomputing or checkpointing the checkpoint tensor. In some implementations, the compiler can determine a recompute ratio of the recompute cost to the memory cost and can compare the recompute ratio to the solution threshold. A computer program product and a computing system can implement aspects of the method.

公开(公告)号：US20220309317A1

公开(公告)日：2022-09-29

申请号：US17364129

申请日：2021-06-30

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06N3/04

Abstract: Disclosed is a method that includes sectioning a graph into a sequence of sections, the sequence of sections including at least a first section followed by a second section. The first section is configured to generate a first output in a first target tiling configuration in response to processing a first input in a first input tiling configuration. The graph is configured to reconfigure the first output in the first target tiling configuration to a second input in a second input tiling configuration. The second section is configured to generate a second output in a second target tiling configuration in response to processing the second input in the second input tiling configuration.

公开(公告)号：US20240069880A1

公开(公告)日：2024-02-29

申请号：US18387906

申请日：2023-11-08

Applicant: SambaNova Systems, Inc.

Inventor： Blaine RISTER ,  Qingjian LI ,  Bowen YANG ,  Junjue WANG ,  Chen LIU ,  Zhuo CHEN ,  Arvind SUJEETH ,  Sumti JAIRATH

IPC: G06F8/41

CPC classification number: G06F8/433

Abstract: In a method a computer-implemented efficiency analyzer selects operators from an intermediate representation of a dataflow program. The operators are included in a mapping of the operators to hardware of a computing system to execute the dataflow program. Based on the mapping and a description of the hardware, the efficiency analyzer computes an execution metric associated with executing the operators on the hardware. Based on the execution metric and hardware description, the efficiency analyzer determines an inefficiency metric, and based on the inefficiency metric, the efficiency analyzer determines an inefficiency associated with the dataflow program. The computing system to execute the dataflow program can comprise a coarse grain computing system and the hardware can include a reconfigurable processor of the computing system. A computer program product and a computing system to a the dataflow program can implement the method.

公开(公告)号：US20230315802A1

公开(公告)日：2023-10-05

申请号：US18128076

申请日：2023-03-29

Applicant: SambaNova Systems, Inc.

Inventor： Junjue WANG ,  Blaine Burton RISTER ,  Zhichao MA ,  Zhuo CHEN ,  Andrew DENG ,  Sumti JAIRATH ,  Arvind Krishna SUJEETH

IPC: G06F17/11

CPC classification number: G06F17/11

Abstract: A method comprises a compiler generating a MI (mixed integer) model to determine mapping decisions to map a dataflow application to hardware of a computing system to execute the application. The MI model comprises MI equations to solve by an MI solver. The MI equations include equations of an objective function corresponding to an optimization objective. The MI equations can comprise decision variables and equations and constraint variables and equations. The compiler outputs the MI model to the MI solver and invokes the MI solver to compute an MI solution comprising solutions to equations among the equations included in the MI model. The compiler receives the MI solution and generates a globally optimized mapping decision based on the MI solution. The MI solver can comprise a commercial program to solve MI linear equations. A computer program product and a computing system can implement the method.

公开(公告)号：US20220309316A1

公开(公告)日：2022-09-29

申请号：US17364110

申请日：2021-06-30

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06N3/04

Abstract: Disclosed is a data processing system that includes compile time logic to section a graph into a sequence of sections including a first section and a second section. The compile time logic is to configure the first section with a first topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the first section, and configure the second section with a second topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the second section. The data processing system further includes runtime logic configured with the compile time logic to execute the first section to generate the inputs, intermediate outputs, and final outputs of the first section in the first topology of tiling configurations, and execute the second section to generate the inputs, intermediate outputs, and final outputs of the second section in the second topology of tiling configurations.

公开(公告)号：US20240168913A1

公开(公告)日：2024-05-23

申请号：US18518695

申请日：2023-11-24

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06F15/78 ,  G06F16/901 ,  G06F17/16

CPC classification number: G06F15/7885 ,  G06F15/7839 ,  G06F16/9024 ,  G06F17/16

Abstract: Disclosed is a method that includes sectioning a graph into a sequence of sections, the sequence of sections including at least a first section followed by a second section. The first section is configured to generate a first output in a first target tiling configuration in response to processing a first input in a first input tiling configuration. The graph is configured to reconfigure the first output in the first target tiling configuration to a second input in a second input tiling configuration. The second section is configured to generate a second output in a second target tiling configuration in response to processing the second input in the second input tiling configuration.

公开(公告)号：US20240078098A1

公开(公告)日：2024-03-07

申请号：US18387912

申请日：2023-11-08

Applicant: SambaNova Systems, Inc.

Inventor： Blaine RISTER ,  Qingjian LI ,  Bowen YANG ,  Junjue WANG ,  Chen LIU ,  Zhuo CHEN ,  Arvind SUJEETH ,  Sumti JAIRATH

IPC: G06F8/41

CPC classification number: G06F8/433

Abstract: In a method, in response to an interface a computer-implemented analysis assistant initiates a presentation of inefficiency results, determined an efficiency analyzer based on a mapping of a dataflow program to execute on hardware of a computing system. The assistant receives an inefficiency included among the inefficiency results and composes formatted inefficiency results comprising a presentation format of the inefficiency to assist a developer of the dataflow program to interpret the inefficiency. The analysis assistant outputs the formatted inefficiency results to an interface, which can comprise an interface to output the formatted inefficiency results for use by the developer to improve the dataflow program in association with the inefficiency. In implementations the presentation can comprise an interactive presentation with a developer of the dataflow program. A computer program product and a computing system can implement the method. The computing system can execute the assistant, and can include the interfaces.

公开(公告)号：US20230315410A1

公开(公告)日：2023-10-05

申请号：US18129714

申请日：2023-03-31

Applicant: SambaNova Systems, Inc.

Inventor： Bowen YANG ,  Zhuo CHEN ,  Chen LIU ,  Fei WANG ,  Ruobing WANG ,  Qinghua Li ,  Weiwei CHEN ,  Junjue WANG ,  Sumti JAIRATH

IPC: G06F8/41

CPC classification number: G06F8/443

Abstract: A method comprises a compiler analyzing a graph to determine a pipeline of operators based on a shared dimension of input and output tensors among the operators. The operators are included in the graph and the graph corresponds to a dataflow application. The compiler determines a tiling decision associated with the pipeline and a tiling cost associated with the tiling decision. The tiling decision can comprise a tile shape to slice tensors of operators of the pipeline. Based on the tiling cost, the compiler determines that the tiling decision improves an optimization objective and includes the pipeline and tiling decision in mapping decisions associated with executing the application on a computing system. The compiler can apply a tiling cost model to determine the tiling costs. A computer program product and a computing system can implement the method.

公开(公告)号：US20230315406A1

公开(公告)日：2023-10-05

申请号：US18129718

申请日：2023-03-31

Applicant: SambaNova Systems, Inc.

Inventor： Blaine RISTER ,  Haocheng DONG ,  David Alan KOEPLINGER ,  Yaqi ZHANG ,  Junjue WANG ,  Zhuo CHEN ,  Arvind SUJEETH

IPC: G06F8/41

CPC classification number: G06F8/433

Abstract: In a method a compiler performs a trial compilation to a low level (LL) intermediate representation (IR) of a high level (HL) decision to execute a dataflow application on a computing system. The LLIR comprises hardware resources to execute the application based on the HL decision and the compiler determines a trial result based on LL execution metrics associated with the trail compilation. The compiler performs a trial compilation of a second HL decision to a second LLIR and determines a trial result based on LL execution metrics associated with the second trail compilation. The compiler evaluates the trial results and, based on the evaluations, selects one or both of the HL decisions for executing the dataflow application. A computer program product and a computing system can implement the method.

公开(公告)号：US20220309325A1

公开(公告)日：2022-09-29

申请号：US17713157

申请日：2022-04-04

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06N3/04

Abstract: A data processing system includes compile time logic to section a graph into a sequence of sections, including a first section followed by a second section. The compile time logic configured the first section to generate a first output in a first non-overlapping target configuration in response to processing an input in a first overlapping input configuration, and configures the second section to generate a second output in a second non-overlapping target configuration in response to processing the first output in a second overlapping input configuration. The compile time logic also creates a set of computer instructions to execute the first section and the second section on a target processing system.