公开(公告)号：US20230315802A1

公开(公告)日：2023-10-05

申请号：US18128076

申请日：2023-03-29

Applicant: SambaNova Systems, Inc.

Inventor： Junjue WANG ,  Blaine Burton RISTER ,  Zhichao MA ,  Zhuo CHEN ,  Andrew DENG ,  Sumti JAIRATH ,  Arvind Krishna SUJEETH

IPC: G06F17/11

CPC classification number: G06F17/11

Abstract: A method comprises a compiler generating a MI (mixed integer) model to determine mapping decisions to map a dataflow application to hardware of a computing system to execute the application. The MI model comprises MI equations to solve by an MI solver. The MI equations include equations of an objective function corresponding to an optimization objective. The MI equations can comprise decision variables and equations and constraint variables and equations. The compiler outputs the MI model to the MI solver and invokes the MI solver to compute an MI solution comprising solutions to equations among the equations included in the MI model. The compiler receives the MI solution and generates a globally optimized mapping decision based on the MI solution. The MI solver can comprise a commercial program to solve MI linear equations. A computer program product and a computing system can implement the method.

公开(公告)号：US20220309316A1

公开(公告)日：2022-09-29

申请号：US17364110

申请日：2021-06-30

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06N3/04

Abstract: Disclosed is a data processing system that includes compile time logic to section a graph into a sequence of sections including a first section and a second section. The compile time logic is to configure the first section with a first topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the first section, and configure the second section with a second topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the second section. The data processing system further includes runtime logic configured with the compile time logic to execute the first section to generate the inputs, intermediate outputs, and final outputs of the first section in the first topology of tiling configurations, and execute the second section to generate the inputs, intermediate outputs, and final outputs of the second section in the second topology of tiling configurations.

公开(公告)号：US20240168913A1

公开(公告)日：2024-05-23

申请号：US18518695

申请日：2023-11-24

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06F15/78 ,  G06F16/901 ,  G06F17/16

CPC classification number: G06F15/7885 ,  G06F15/7839 ,  G06F16/9024 ,  G06F17/16

Abstract: Disclosed is a method that includes sectioning a graph into a sequence of sections, the sequence of sections including at least a first section followed by a second section. The first section is configured to generate a first output in a first target tiling configuration in response to processing a first input in a first input tiling configuration. The graph is configured to reconfigure the first output in the first target tiling configuration to a second input in a second input tiling configuration. The second section is configured to generate a second output in a second target tiling configuration in response to processing the second input in the second input tiling configuration.

公开(公告)号：US20240020265A1

公开(公告)日：2024-01-18

申请号：US18221685

申请日：2023-07-13

Applicant: SambaNova Systems, Inc.

Inventor： Yue FU ,  Kin Hing LEUNG ,  Likun HAO ,  Arvind Krishna SUJEETH ,  Sumti JAIRATH ,  Andrew DENG ,  Chris RÉ ,  Raghu PRABHAKAR

IPC: G06F15/78

CPC classification number: G06F15/7871

Abstract: A system with a cost estimation tool for estimating a realized bandwidth consumption of a logical edge between a logical producer unit and a logical consumer unit of an operation unit graph during placement and routing of the logical producer unit, the logical consumer unit, and the logical edge onto a reconfigurable processor is presented as well as a method of operating such a cost estimation tool and a non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate such a cost estimation tool The cost estimation tool may be configured to determine the realized bandwidth consumption of the tentative assignment based on an upper bandwidth limit of the logical edge, an end-to-end bandwidth, a scaling factor of a realized bandwidth, and a congestion estimation of the physical link.

公开(公告)号：US20240020264A1

公开(公告)日：2024-01-18

申请号：US18221683

申请日：2023-07-13

Applicant: SambaNova Systems, Inc.

Inventor： Yue FU ,  Kin Hing LEUNG ,  Joshua BROT ,  Arvind Krishna SUJEETH ,  Sumti JAIRATH ,  Andrew DENG ,  Chris RÉ ,  Raghu PRABHAKAR

IPC: G06F15/78

CPC classification number: G06F15/7871

Abstract: A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for determining scaled logical edge bandwidths in an operation unit graph in preparation of placing and routing the operation unit graph onto a reconfigurable processor. The cost estimation tool may be configured to receive the operation unit graph, divide the operation unit graph in first and second subgraphs, determine maximum latencies of the first and second subgraphs, and determine a scaled logical edge bandwidth of a logical edge that couples a first logical unit of M logical units in the first subgraph with a second logical unit of N logical units in the first subgraph based on M, N, and scaled bandwidth limits of the M and N logical units.

公开(公告)号：US20230315407A1

公开(公告)日：2023-10-05

申请号：US18129722

申请日：2023-03-31

Applicant: SambaNova Systems, Inc.

Inventor： Bowen YANG ,  Zhuo CHEN ,  Fei WANG ,  Venkat Krishna SRINIVASAN ,  Chen LIU ,  Junjue WANG ,  Arvind Krishna SUJEETH ,  Sumti JAIRATH

IPC: G06F8/41

CPC classification number: G06F8/433

Abstract: According to a computing method a compiler determines a recompute node included in a dataflow application and a checkpoint tensor produced by the recompute node. The compiler determines a recompute cost to recompute the checkpoint tensor, and a memory cost to checkpoint the checkpoint tensor in a memory. Based on the recompute cost and/or the memory cost, the compiler determines a solution cost and compares the solution cost to a solution threshold. Based on comparing the solution cost to the solution threshold, the compiler determines a checkpoint solution to execute the dataflow application. The checkpoint solution can comprise recomputing or checkpointing the checkpoint tensor. In some implementations, the compiler can determine a recompute ratio of the recompute cost to the memory cost and can compare the recompute ratio to the solution threshold. A computer program product and a computing system can implement aspects of the method.

公开(公告)号：US20220309317A1

公开(公告)日：2022-09-29

申请号：US17364129

申请日：2021-06-30

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06N3/04

Abstract: Disclosed is a method that includes sectioning a graph into a sequence of sections, the sequence of sections including at least a first section followed by a second section. The first section is configured to generate a first output in a first target tiling configuration in response to processing a first input in a first input tiling configuration. The graph is configured to reconfigure the first output in the first target tiling configuration to a second input in a second input tiling configuration. The second section is configured to generate a second output in a second target tiling configuration in response to processing the second input in the second input tiling configuration.

公开(公告)号：US20240020170A1

公开(公告)日：2024-01-18

申请号：US18221678

申请日：2023-07-13

Applicant: SambaNova Systems, Inc.

Inventor： Yue FU ,  Kin Hing LEUNG ,  Arvind Krishna SUJEETH ,  Sumti JAIRATH ,  Andrew DENG ,  Chris RÉ ,  Raghu PRABHAKAR

IPC: G06F9/50 ,  G06F13/40

CPC classification number: G06F9/5044 ,  G06F13/4063

Abstract: A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for estimating a cost of implementing an operation unit graph. The operation unit graph may include first and second logical units that perform first and second data operations and have first and second ports, respectively, coupled by a logical edge, on a reconfigurable processor. The method includes receiving the operation unit graph, determining first and second upper bandwidth limits of the first and second ports, respectively, determining a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits, determining a timing group for the logical edge, and providing the logical edge bandwidth and the timing group as a cost estimation of implementing the operation unit graph on the reconfigurable processor.

公开(公告)号：US20220309325A1

公开(公告)日：2022-09-29

申请号：US17713157

申请日：2022-04-04

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06N3/04

Abstract: A data processing system includes compile time logic to section a graph into a sequence of sections, including a first section followed by a second section. The compile time logic configured the first section to generate a first output in a first non-overlapping target configuration in response to processing an input in a first overlapping input configuration, and configures the second section to generate a second output in a second non-overlapping target configuration in response to processing the first output in a second overlapping input configuration. The compile time logic also creates a set of computer instructions to execute the first section and the second section on a target processing system.

公开(公告)号：US20220309324A1

公开(公告)日：2022-09-29

申请号：US17700452

申请日：2022-03-21

Applicant: SambaNova Systems, Inc.

Inventor： Tejas Nagendra Babu NAMA ,  Ruddhi CHAPHEKAR ,  Ram SIVARAMAKRISHNAN ,  Raghu PRABHAKAR ,  Sumti JAIRATH ,  Junjue WANG ,  Kaizhao LIANG ,  Adi FUCHS ,  Matheen MUSADDIQ ,  Arvind Krishna SUJEETH

IPC: G06N3/04

Abstract: A processing graph of an application with a sequence of processing nodes is obtained which processes an input and generates an intermediate representation a further intermediate representation, and an output representation of the input at stages in the sequence of processing nodes. Graph metadata is generated that specifies a non-overlapping target tiling configuration for the output representation, an overlapping tiling configuration for the input, an overlapping tiling configuration for the intermediate representation, and a third tiling configuration for the further intermediate representation. The processing graph is modified based on the graph metadata to conform to the parameters specified by the graph metadata. A set of computer instructions is then created to execute the modified processing graph on a target processing system.