公开(公告)号：US20130262072A1

公开(公告)日：2013-10-03

申请号：US13435707

申请日：2012-03-30

申请人： Sameth W. Asaad ,  Mohit Kapur

发明人： Sameth W. Asaad ,  Mohit Kapur

IPC分类号： G06F17/50

CPC分类号： G01R31/31703 ,  G01R31/2851 ,  G01R31/31727 ,  G01R31/3177 ,  G06F17/5027

摘要： A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

摘要翻译： 公开了一种使用现场可编程门阵列（FPGA）来模拟待测器件（DUT）的操作的方法，系统和计算机程序产品。 DUT包括具有多个输入端口的设备存储器，并且FPGA与具有第二数量的输入端口的目标存储器相关联，第二数量小于第一数量。 在一个实施例中，给定的一组输入以频率Fd和定义的时间周期被施加到设备存储器，并且给定的一组输入以频率Ft被施加到目标存储器。 Ft大于Fd，并且在设备存储器和目标存储器之间保持循环精度。 在一个实施例中，通过将DUT存储器接口协议与目标存储器存储阵列分离来创建DUT存储器的周期精确模型。

公开(公告)号：US09230046B2

公开(公告)日：2016-01-05

申请号：US13435614

申请日：2012-03-30

申请人： Sameth W. Asaad ,  Mohit Kapur

发明人： Sameth W. Asaad ,  Mohit Kapur

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5027 ,  G06F9/455

摘要： A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

摘要翻译： 公开了一种方法，系统和计算机程序产品，用于为用于模拟被测器件（DUT）的操作的循环精确的基于FPGA的硬件加速器生成时钟信号。 在一个实施例中，DUT包括多个器件时钟，以多个频率和定义的频率比产生多个器件时钟信号; 并且FPG硬件加速器包括多个加速器时钟，产生多个加速器时钟信号以操作FPGA硬件加速器来模拟DUT的操作。 在一个实施例中，DUT的操作被映射到FPGA硬件加速器，并且加速器时钟信号以多个频率和定义的多个器件时钟频率的频率比生成，以保持DUT和DUT之间的周期精度 FPGA硬件加速器。 在一个实施例中，可以使用FPGA硬件加速器来控制多个设备时钟的频率。

公开(公告)号：US20130262073A1

公开(公告)日：2013-10-03

申请号：US13435614

申请日：2012-03-30

申请人： Sameth W. Asaad ,  Mohit Kapur

发明人： Sameth W. Asaad ,  Mohit Kapur

IPC分类号： G06F17/50

CPC分类号： G06F17/5027 ,  G06F9/455

摘要： A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

摘要翻译： 公开了一种方法，系统和计算机程序产品，用于为用于模拟被测器件（DUT）的操作的循环精确的基于FPGA的硬件加速器生成时钟信号。 在一个实施例中，DUT包括多个器件时钟，以多个频率和定义的频率比产生多个器件时钟信号; 并且FPG硬件加速器包括多个加速器时钟，产生多个加速器时钟信号以操作FPGA硬件加速器来模拟DUT的操作。 在一个实施例中，DUT的操作被映射到FPGA硬件加速器，并且加速器时钟信号以多个频率和定义的多个器件时钟频率的频率比生成，以保持DUT和DUT之间的周期精度 FPGA硬件加速器。 在一个实施例中，可以使用FPGA硬件加速器来控制多个设备时钟的频率。