DISPLAY DEVICE
    1.
    发明公开
    DISPLAY DEVICE 审中-公开

    公开(公告)号:US20230276660A1

    公开(公告)日:2023-08-31

    申请号:US18140530

    申请日:2023-04-27

    CPC classification number: H10K59/1213 H10K59/40 G09G2300/0426 G09G3/3233

    Abstract: A display device includes: a substrate; and a semiconductor layer disposed on the substrate, and including a first area, a second area, and a third area that are sequentially positioned by dividing the semiconductor layer into three areas in a thickness direction of the semiconductor layer, wherein the semiconductor layer includes polycrystalline silicon, a concentration of fluorine contained in the semiconductor layer has a first peak value in the first area and a second peak value in the third area, and the first peak value of the concentration of the fluorine in the semiconductor layer is about 30% or less of the second peak value of the concentration of the fluorine in the semiconductor layer.

    DISPLAY DEVICE
    2.
    发明申请

    公开(公告)号:US20220028947A1

    公开(公告)日:2022-01-27

    申请号:US17373602

    申请日:2021-07-12

    Abstract: A display device includes: a substrate; and a semiconductor layer disposed on the substrate, and including a first area, a second area, and a third area that are sequentially positioned by dividing the semiconductor layer into three areas in a thickness direction of the semiconductor layer, wherein the semiconductor layer includes polycrystalline silicon, a concentration of fluorine contained in the semiconductor layer has a first peak value in the first area and a second peak value in the third area, and the first peak value of the concentration of the fluorine in the semiconductor layer is about 30% or less of the second peak value of the concentration of the fluorine in the semiconductor layer.

    THIN FILM TRANSISTOR, MANUFACTURING METHOD OF THE SAME, AND DISPLAY DEVICE HAVING THE SAME

    公开(公告)号:US20240136443A1

    公开(公告)日:2024-04-25

    申请号:US18492927

    申请日:2023-10-23

    Abstract: A transistor may include a first insulating layer disposed on a substrate, a dummy layer disposed on the first insulating layer, a semiconductor layer disposed on the dummy layer, the semiconductor layer including a first area, a second area, and a channel area disposed between the first and second areas, a second insulating layer disposed on the semiconductor layer, a gate electrode overlapping the channel area with the second insulating interposed therebetween, a third insulating layer disposed over the gate electrode, a first electrode disposed on the third insulating layer, the first electrode being electrically connected to the first area, and a second electrode disposed on the third insulating layer spaced apart from the first electrode, the second electrode being electrically connected to the second area. The dummy layer may include indium oxide, and the semiconductor layer may include indium gallium zinc oxide.

    DISPLAY DEVICE
    4.
    发明申请

    公开(公告)号:US20250024708A1

    公开(公告)日:2025-01-16

    申请号:US18904654

    申请日:2024-10-02

    Abstract: A display device includes: a substrate; and a semiconductor layer disposed on the substrate, and including a first area, a second area, and a third area that are sequentially positioned by dividing the semiconductor layer into three areas in a thickness direction of the semiconductor layer, wherein the semiconductor layer includes polycrystalline silicon, a concentration of fluorine contained in the semiconductor layer has a first peak value in the first area and a second peak value in the third area, and the first peak value of the concentration of the fluorine in the semiconductor layer is about 30% or less of the second peak value of the concentration of the fluorine in the semiconductor layer.

    THIN FILM TRANSISTOR, MANUFACTURING METHOD OF THE SAME, AND DISPLAY DEVICE HAVING THE SAME

    公开(公告)号:US20240234580A9

    公开(公告)日:2024-07-11

    申请号:US18492927

    申请日:2023-10-24

    Abstract: A transistor may include a first insulating layer disposed on a substrate, a dummy layer disposed on the first insulating layer, a semiconductor layer disposed on the dummy layer, the semiconductor layer including a first area, a second area, and a channel area disposed between the first and second areas, a second insulating layer disposed on the semiconductor layer, a gate electrode overlapping the channel area with the second insulating interposed therebetween, a third insulating layer disposed over the gate electrode, a first electrode disposed on the third insulating layer, the first electrode being electrically connected to the first area, and a second electrode disposed on the third insulating layer spaced apart from the first electrode, the second electrode being electrically connected to the second area. The dummy layer may include indium oxide, and the semiconductor layer may include indium gallium zinc oxide.

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