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公开(公告)号：US11978394B2
公开(公告)日：2024-05-07
申请号：US17246430
申请日：2021-04-30
Applicant: Samsung Display Co., Ltd.
Inventor： Taehoon Kim , Soon-Dong Kim , Jaekeun Lim , Joon-Chul Goh , Bonghyun You
IPC: G09G3/3225 , H10K59/121
CPC classification number: G09G3/3225 , H10K59/121 , G09G2330/021
Abstract: A display device includes: a first partial emission driver configured to provide first emission control signals to a first partial panel area of the display panel, and a second partial emission driver configured to provide second emission control signals to a second partial panel area of the display panel; and a power management block configured to: provide a first voltage and a second voltage to the emission driver, in response to the first partial emission driver generating the first emission control signals; and provide a third voltage and a fourth voltage to the emission driver in response to the second partial emission driver generating the second emission control signals; and an emission control block configured to receive the first voltage and the second voltage from the power management block and to provide a first clock signal and a second clock signal to the emission driver.
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公开(公告)号：US11961463B2
公开(公告)日：2024-04-16
申请号：US18196137
申请日：2023-05-11
Applicant: Samsung Display Co., LTD.
Inventor： Jin-Wook Yang , Yu-Chol Kim , Donggyu Lee , Jaekeun Lim , Jae-Hyeon Jeon
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2310/0216 , G09G2310/0267 , G09G2330/028
Abstract: A pixel connected to a first scan line includes a light-emitting element including an anode and a cathode, a first transistor including a first electrode, a second electrode, and a gate electrode connected to a first node, a first capacitor connected between the first node and a second node, a second transistor connected between the second electrode of the first transistor and the first node including a gate electrode connected to the first scan line, a third transistor including a first electrode, a second electrode connected to the second node, and a gate electrode connected to the first scan line, and a fourth transistor including a first electrode connected to a first driving voltage line, a second electrode connected to the first electrode of the first transistor, and a gate electrode connected to the first scan line.
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公开(公告)号：US11436985B2
公开(公告)日：2022-09-06
申请号：US17315449
申请日：2021-05-10
Applicant: Samsung Display Co., Ltd.
Inventor： Sehyuk Park , Hongsoo Kim , Jinyoung Roh , Hyojin Lee , Jaekeun Lim , Junheyung Jung
IPC: G09G3/3291 , G09G3/20
Abstract: A display apparatus includes a display panel including pixels, a gate driver applying a gate signal to a gate line, a data driver applying a data voltage to a data line and a driving controller determining a mode of an input image data to a moving image mode or a static image mode according to whether the input image data is a moving image or a static image, driving the display panel in a moving image driving frequency in the moving image mode and in a static image driving frequency in the static image mode, operating the gate driver in an alternate driving mode such that the gate driver scans a first group of the gate lines in a first duration and a second group of the gate lines in a second duration and inserting a compensation frame to scan all of the gate lines when an image transition is occurred in the static image mode.
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公开(公告)号：US20200150805A1
公开(公告)日：2020-05-14
申请号：US16573539
申请日：2019-09-17
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Jeonkyoo Kim , Dong Won Lee , Jaekeun Lim
Abstract: A display device includes a display panel that includes a plurality of pixels, a touch panel that includes a plurality of driving lines and a plurality of sensing lines, a display driver that drives the display panel at a first display frame rate in a normal driving mode, and that drives the display panel at a second display frame rate lower than the first display frame rate in a low power driving mode, and a touch controller that drives the touch panel with a mutual capacitance sensing method in the normal driving mode, and that drive the touch panel with a self capacitance sensing method in the low power driving mode.
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公开(公告)号：US10607519B2
公开(公告)日：2020-03-31
申请号：US14980581
申请日：2015-12-28
Applicant: Samsung Display Co., Ltd
Inventor： Jaekeun Lim , Chongchul Chai , Jonghee Kim
Abstract: Provided is a display device. The display device includes a display panel, a gate driving circuit, a sensor part, and a control voltage generator. The gate driving circuit includes driving transistors including a first control electrode and a second control electrode. The sensor part is configured to measure an environmental factor that changes a threshold voltage of the driving transistors. The control voltage generator is configured to apply to the second control electrode a control voltage for controlling the threshold voltage of the driving transistors on the basis of the environmental factor measured by the sensor part.
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Patent Agency Ranking
公开(公告)号：US09542889B2
公开(公告)日：2017-01-10
申请号：US14478530
申请日：2014-09-05
Applicant: Samsung Display Co., Ltd.
Inventor： Cheol-Gon Lee , Kyoungju Shin , Chongchul Chai , HyunJoon Kim , Jaekeun Lim
CPC classification number: G09G3/3266 , G09G3/3677 , G09G2300/0413 , G09G2300/043 , G09G2310/0213 , G09G2310/0251 , G09G2310/0289 , G09G2320/0223 , G09G2320/103 , G09G2330/023 , G11C19/28
Abstract: A display device is disclosed. In one aspect, the display device includes a timing controller configured to receive an image signal and a control signal and output a mode signal and a gate pulse signal based on the image signal and the control signal, wherein the mode signal has a voltage level and wherein the gate pulse signal has a frequency. The display device further includes a clock generator configured to generate a gate clock signal based on the mode signal and the gate pulse signal, wherein the gate clock signal has a voltage level and wherein the clock generator is further configured to set the voltage level of the gate clock signal based at least in part on the mode signal. The display device includes gate lines and a gate driver configured to drive gate lines based at least in part on the gate clock signal.
Abstract translation: 公开了一种显示装置。 一方面，显示装置包括定时控制器，其被配置为基于图像信号和控制信号接收图像信号和控制信号并输出模式信号和门脉冲信号，其中模式信号具有电压电平，以及 其中所述栅极脉冲信号具有频率。 所述显示装置还包括时钟发生器，其被配置为基于所述模式信号和所述门脉冲信号产生栅极时钟信号，其中所述栅极时钟信号具有电压电平，并且其中所述时钟发生器还被配置为将所述栅极时钟信号 栅极时钟信号至少部分地基于模式信号。 显示装置包括栅极线和栅极驱动器，栅极驱动器被配置为至少部分地基于栅极时钟信号来驱动栅极线。
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公开(公告)号：US09201258B2
公开(公告)日：2015-12-01
申请号：US13945316
申请日：2013-07-18
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Yeun Tae Kim , Hee-Keun Lee , Jaekeun Lim
IPC: H01L33/08 , G02F1/1333 , G02F1/167
CPC classification number: G09G3/3607 , G02F1/133377 , G02F2001/1672 , G09G3/3655 , G09G2310/027 , H04N9/30
Abstract: A display device includes a substrate and pixels arranged on the substrate in a matrix form. The substrate includes a display area in which the pixels are arranged and a non-display area disposed adjacent to a side of the display area. Each pixel includes a cover layer that extends in a row direction that includes a sidewall portion connected to the substrate and a cover portion spaced apart from the substrate and connected to the sidewall portion to define a tunnel-shaped cavity on the substrate. A width of the sidewall portion between adjacent pixels is less than a width of the sidewall portion disposed at an outermost position, and the cover layer seals one side of the tunnel-shaped cavity in the pixels arranged in a first row and a last row.
Abstract translation: 显示装置包括基板和以矩阵形式布置在基板上的像素。 衬底包括其中布置像素的显示区域和邻近显示区域设置的非显示区域。 每个像素包括覆盖层，其沿行方向延伸，包括连接到衬底的侧壁部分和与衬底间隔开并连接到侧壁部分的盖部分，以在衬底上限定隧道形空腔。 相邻像素之间的侧壁部分的宽度小于设置在最外侧位置处的侧壁部分的宽度，并且覆盖层密封布置在第一行和最后一行中的像素中的隧道形空腔的一侧。
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公开(公告)号：US12260827B2
公开(公告)日：2025-03-25
申请号：US18323887
申请日：2023-05-25
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Jinyoung Roh , Bon-Seog Gu , Hae-Kwan Seo , Jaekeun Lim
IPC: G09G3/3266 , G09G3/20 , G09G3/32
Abstract: A display device includes a display panel, a scan driver outputting a scan signal, and a data driver. The scan driver includes a first sub-scan driver that receives a first start signal and an odd clock signal, and a second sub-scan driver that receives a second start signal and an even clock signal. The scan signal has an activation period corresponding to a horizontal period. The odd clock signal includes a first clock enable period and a first clock disable period, which are ‘k’ times greater than the horizontal period. The even clock signal includes a second clock enable period and a second clock disable period, which are ‘k’ times greater than the horizontal period. The first clock enable period and the second clock enable period alternate with one another.
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公开(公告)号：US12211424B2
公开(公告)日：2025-01-28
申请号：US18418890
申请日：2024-01-22
Applicant: Samsung Display Co., LTD.
Inventor： Taehoon Kim , Sangan Kwon , Soon-Dong Kim , Geunjeong Park , Changnoh Yoon , Jaekeun Lim
Abstract: A display panel driving circuit includes a scan driving circuit including a scan stage and a timing controller. The scan stage includes a first circuit connected to a first input node of receiving a first clock signal, a second circuit connected to a second input node of receiving a second clock signal, a third circuit connected to a third input node of receiving a carry signal, the first circuit, and the second circuit and connected to a first control node and a second control node, a pull-up transistor electrically connected to the first input node and an output node of outputting a scan signal and turned on/off by the first control node, and a pull-down transistor electrically connected to the output node and a low-level voltage line and turned on/off by the second control node.
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公开(公告)号：US12020635B1
公开(公告)日：2024-06-25
申请号：US18227975
申请日：2023-07-31
Applicant: Samsung Display Co., Ltd.
Inventor： Jinyoung Roh , Hae-Kwan Seo , Bon-Seog Gu , Jaekeun Lim
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2310/0275 , G09G2310/0297 , G09G2330/021
Abstract: A display panel of a display device includes first and second pixel circuits disposed in a first row and connected to 0-th and second data lines, respectively, third and fourth pixel circuits disposed in a second row and connected to first and third data lines, respectively, a first light-emitting area connected to the first pixel circuit via a first connection wiring, a second light-emitting area at least partially overlapping the second pixel circuit and connected to the second pixel circuit, a third light-emitting area at least partially overlapping the third pixel circuit and connected to the third pixel circuit, and a fourth light-emitting area connected to the fourth pixel circuit via a second connection wiring.
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