公开(公告)号：US20220293045A1

公开(公告)日：2022-09-15

申请号：US17827272

申请日：2022-05-27

Applicant: Samsung Display Co., Ltd.

Inventor： Yang Hwa CHOI ,  Bo Yong CHUNG

IPC: G09G3/32 ,  G09G3/3266

Abstract: A scan driver includes a first transistor including gate, first, and second electrodes coupled to a Q node, a scan clock line, and a scan line. A second transistor includes gate and first electrodes coupled to a scan carry line, and a second electrode coupled to the Q node. A third transistor includes gate and first electrodes coupled to a first control line and a sensing carry line. A fourth transistor includes a gate and first electrode coupled to the sensing carry line and the third transistor first electrode. A fifth transistor includes gate, first, and second electrodes coupled to a fourth transistor second electrode, a second control line, and a node. A capacitor includes first and second electrodes coupled to the fifth transistor first and gate electrodes. A sixth transistor includes gate, first, and second electrodes coupled to a third control line, the node, and the Q node.

公开(公告)号：US20200258446A1

公开(公告)日：2020-08-13

申请号：US16781187

申请日：2020-02-04

Applicant: Samsung Display Co., Ltd.

Inventor： Yang Hwa CHOI ,  Sun Kwang KIM ,  Sang Jin JEON

IPC: G09G3/32

Abstract: A scan driver includes two or more scan signal output circuits (SSOC), each being coupled to a first scan line (FSL) and a second scan line (SSL), and including a driving circuit, a first buffer circuit (FBC), and a second buffer circuit (SBC). The driving circuit applies a first driving signal (DS) to a first driving node (DN) and applies a second DS to a second DN based on an input signal, a clock signal (CS), a display-on signal, and an on-level voltage. The input signal is a scan start signal or a previous scan signal. The FBC outputs a sensing signal to the SSL based on the first DS, the second DS, an off-level voltage, and a sensing CS. The SBC outputs a scan signal to the FSL based on the first DS, the second DS, the off-level voltage, and a scan CS.

公开(公告)号：US20190148477A1

公开(公告)日：2019-05-16

申请号：US16189270

申请日：2018-11-13

Applicant: Samsung Display Co., Ltd.

Inventor： Jun Hyun PARK ,  Cheol Gon LEE ,  Chong Chul CHAI ,  Yang Hwa CHOI

IPC: H01L27/32

Abstract: A display device includes: an initialization power line extending along a first direction; a scan line extending along the first direction and spaced apart from the initialization power line, a data line and a driving voltage line insulated from the initialization power line and the scan line and extending along the second direction; a first switching element including a first electrode connected to the driving voltage line, a first gate electrode overlapping the initialization power line, and a second electrode; a second switching element including a third electrode connected to the first gate electrode, a second gate electrode connected to the scan line, and a fourth electrode; a third switching element including a fifth electrode connected to the fourth electrode, a third gate electrode connected to the initialization power line, and a sixth electrode connected to the second electrode; and a light emitting element connected to the second electrode.

公开(公告)号：US20210074220A1

公开(公告)日：2021-03-11

申请号：US16903307

申请日：2020-06-16

Applicant: Samsung Display Co., LTD.

Inventor： Jong Hee KIM ,  Tak Young LEE ,  Bo Yong CHUNG ,  Yang Hwa CHOI

IPC: G09G3/3266 ,  G09G3/3258

Abstract: A scan driver including a plurality of scan stages. A first scan stage among the plurality of scan stages includes first-to-sixth transistors and a first capacitor. The first transistor is connected to a first Q node, a first scan clock line, and a first scan line. A second transistor is connected to a first scan carry line and the first Q node. A third transistor is connected to a first sensing carry line and a second sensing carry line. A fourth transistor is connected to a first control line and the third transistor. A fifth transistor is connected to the fourth transistor, a second control line, and a first node. A first capacitor is connected to the fifth transistor. A sixth transistor is connected to a third control line, the first node, and the first Q node.

公开(公告)号：US20200090595A1

公开(公告)日：2020-03-19

申请号：US16569027

申请日：2019-09-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun Hyun PARK ,  Sun Kwang KIM ,  Young Wan SEO ,  Cheol Gon LEE ,  Yang Hwa CHOI

IPC: G09G3/3291 ,  G09G3/3266 ,  G09G3/3233 ,  G09G3/3258

Abstract: A display device includes an initialization voltage line to which an initialization voltage is applied, a first driving voltage line to which a first driving voltage is applied, and a pixel connected to the initialization voltage line and the first driving voltage line. The pixel includes a first transistor to control a driving current flowing between a first electrode and a second electrode according to a voltage applied to a first node, a light emitting element between the first transistor and the first driving voltage line, and a first capacitor between the first node and the initialization voltage line. During an initialization period in which the light emitting element is initialized, the initialization voltage is changed from a first level voltage to a second level voltage lower than the first level voltage and the first driving voltage is changed from a first high-level voltage to a first low-level voltage.

公开(公告)号：US20220335881A1

公开(公告)日：2022-10-20

申请号：US17517734

申请日：2021-11-03

Applicant: Samsung Display Co., Ltd.

Inventor： Hyuk KIM ,  Yang Hwa CHOI ,  Jung Hwan HWANG

IPC: G09G3/32

Abstract: A display device of the present inventive concept includes a processor supplying grayscale data in active periods of frame periods and stopping supply of the grayscale data in blank periods of the frame periods; a switch controller generating a first switch control signal when a blank period is longer than a predetermined period, and generating a second switch control signal when the blank period ends; a power supply supplying a voltage different from a first power voltage to a first power line when the first switch control signal is received and supplying the first power voltage to the first power line when the second switch control signal is received; and pixels commonly connected to the first power line.

公开(公告)号：US20220139327A1

公开(公告)日：2022-05-05

申请号：US17577301

申请日：2022-01-17

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee KIM ,  Tak Young LEE ,  Bo Yong CHUNG ,  Yang Hwa CHOI

IPC: G09G3/3266 ,  G09G3/3258

Abstract: A scan driver including a plurality of scan stages. A first scan stage among the plurality of scan stages includes first-to-sixth transistors and a first capacitor. The first transistor is connected to a first Q node, a first scan clock line, and a first scan line. A second transistor is connected to a first scan carry line and the first Q node. A third transistor is connected to a first sensing carry line and a second sensing carry line. A fourth transistor is connected to a first control line and the third transistor. A fifth transistor is connected to the fourth transistor, a second control line, and a first node. A first capacitor is connected to the fifth transistor. A sixth transistor is connected to a third control line, the first node, and the first Q node.

公开(公告)号：US20210383748A1

公开(公告)日：2021-12-09

申请号：US17409707

申请日：2021-08-23

Applicant: Samsung Display Co., Ltd.

Inventor： Yang Hwa CHOI ,  Sun Kwang Kim ,  Sang Jin JEON

IPC: G09G3/32

Abstract: A scan driver includes two or more scan signal output circuits (SSOC), each being coupled to a first scan line (FSL) and a second scan line (SSL), and including a driving circuit, a first buffer circuit (FBC), and a second buffer circuit (SBC). The driving circuit applies a first driving signal (DS) to a first driving node (DN) and applies a second DS to a second DN based on an input signal, a clock signal (CS), a display-on signal, and an on-level voltage. The input signal is a scan start signal or a previous scan signal. The FBC outputs a sensing signal to the SSL based on the first DS, the second DS, an off-level voltage, and a sensing CS. The SBC outputs a scan signal to the FSL based on the first DS, the second DS, the off-level voltage, and a scan CS.

公开(公告)号：US20240029642A1

公开(公告)日：2024-01-25

申请号：US18375566

申请日：2023-10-02

Applicant: Samsung Display Co., Ltd.

Inventor： Yang Hwa CHOI ,  Bo Yong CHUNG

IPC: G09G3/32 ,  G09G3/3266

CPC classification number: G09G3/32 ,  G09G3/3266 ,  G09G2310/06 ,  G09G2310/0264 ,  G09G2310/0286 ,  G09G2300/0852

Abstract: A scan driver includes a first transistor including gate, first, and second electrodes coupled to a Q node, a scan clock line, and a scan line. A second transistor includes gate and first electrodes coupled to a scan carry line, and a second electrode coupled to the Q node. A third transistor includes gate and first electrodes coupled to a first control line and a sensing carry line. A fourth transistor includes a gate and first electrode coupled to the sensing carry line and the third transistor first electrode. A fifth transistor includes gate, first, and second electrodes coupled to a fourth transistor second electrode, a second control line, and a node. A capacitor includes first and second electrodes coupled to the fifth transistor first and gate electrodes. A sixth transistor includes gate, first, and second electrodes coupled to a third control line, the node, and the Q node.

公开(公告)号：US20210241669A1

公开(公告)日：2021-08-05

申请号：US17238166

申请日：2021-04-22

Applicant: Samsung Display Co., Ltd.

Inventor： Yang Hwa CHOI ,  Sun Kwang KIM ,  Sang Jin JEON

IPC: G09G3/20

Abstract: A scan driver for a display device includes scan signal output circuits connected to each other through scan lines. Each scan signal output circuit includes: a drive circuit to apply a first drive signal to a first drive node, to apply a second drive signal to a second drive node, and to apply a connection signal to a connection signal output node based on i) an input signal which is one of either a scan start signal or a scan signal applied by another scan signal output circuit, ii) a clock signal, and iii) an on-level voltage; and a buffer circuit to receive the connection signal, the first drive signal, and the second drive signal from the drive circuit, and to output one of scan signals to one of the scan lines based on the first drive signal, the second drive signal, and the clock signal.