公开(公告)号：US20170243553A1

公开(公告)日：2017-08-24

申请号：US15439647

申请日：2017-02-22

Applicant: Samsung Display Co., LTD. ,  Sogang University Research Foundation

Inventor： Sang-Kuk KIM ,  Weon-Jun CHOE ,  Moon-Sang HWANG ,  Tai-Ji AN ,  Seung-Hoon LEE ,  Won-Kang KIM ,  Jun-Sang PARK

IPC: G09G3/36 ,  G09G3/3258

CPC classification number: G09G3/3648 ,  G09G3/20 ,  G09G3/3258 ,  G09G2310/027 ,  G09G2310/08

Abstract: A digital-to-analog converter may include a converting unit and a distributing unit. The converting unit may generate a first analog signal set based on less-than-all bits of an image data set in a first period and may generate a second analog signal set based on all bits of the image data set in a second period. The all bits may include at least 2 bits. The distributing unit may include output terminals, may distribute the first analog signal set to the output terminals in a first sequence in the first period, and may distribute the second analog signal to the output terminals in a second sequence. The second sequence may be opposite to the first sequence.

公开(公告)号：US20180211605A1

公开(公告)日：2018-07-26

申请号：US15879337

申请日：2018-01-24

Applicant: Samsung Display Co., Ltd. ,  Sogang University Research & Business Development Foundation

Inventor： Sang Kuk KIM ,  Moonsang HWANG ,  Weonjun CHOE ,  Tai-Ji AN ,  Seung-Hoon LEE ,  Won-Kang KIM ,  Jun-Sang PARK

IPC: G09G3/3275

CPC classification number: G09G3/3275 ,  G09G3/3685 ,  G09G3/3696 ,  G09G2310/0243 ,  G09G2310/0259 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/0294 ,  G09G2310/066 ,  G09G2330/08

Abstract: A data driver includes a ramp signal generator generating a first ramp signal and a second ramp signal, a counter generating a count signal based on a clock signal, and channels each generating a data signal based on the first ramp signal, the second ramp signal, and the count signal. Each channel includes a latch circuit dividing the image data into a first partial data and a second partial data and latching the first and the second partial data, a duplication driver generating first and second reference signals by duplicating the first and second ramp signals, a digital-analog converter generating a driving signal corresponding to a first partial data based on the first and second reference signals, and an output circuit sampling the driving signal by comparing the second partial data with the count signal to output the data signal.