公开(公告)号：US20150287392A1

公开(公告)日：2015-10-08

申请号：US14456926

申请日：2014-08-11

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee KIM ,  Hyun Joon KIM ,  Kyoung Ju SHIN ,  Alexander WARD ,  Cheol-Gon LEE ,  Chong Chul CHAI

IPC: G09G5/18 ,  G09G3/36 ,  H03K17/693

CPC classification number: H03K17/693 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/06

Abstract: A stage includes a first transistor including an input terminal to which a clock signal is applied and a control terminal connected to a first node; a first capacitor including terminals respectively connected to the first node and an output terminal of the first transistor; a second transistor including an input terminal connected to the output terminal of the first transistor, a control terminal connected to a second node, and an output terminal to which a low voltage is applied; a third transistor including an output terminal connected to the second node, a control terminal connected to the first node, and an input terminal to which the low voltage is applied; and a fourth transistor including an input terminal connected to the first node and an output terminal to which the low voltage is applied, wherein the fourth transistor is switched according to an output signal of a next stage.

Abstract translation: 舞台包括：第一晶体管，包括施加时钟信号的输入端子和连接到第一节点的控制端子; 第一电容器，包括分别连接到第一节点的端子和第一晶体管的输出端子; 第二晶体管，包括连接到第一晶体管的输出端子的输入端子，连接到第二节点的控制端子和施加低电压的输出端子; 第三晶体管，包括连接到第二节点的输出端子，连接到第一节点的控制端子和施加低电压的输入端子; 以及第四晶体管，其包括连接到所述第一节点的输入端子和施加所述低电压的输出端子，其中所述第四晶体管根据下一级的输出信号被切换。