公开(公告)号：US09685948B2

公开(公告)日：2017-06-20

申请号：US14456926

申请日：2014-08-11

Applicant: Samsung Display Co., Ltd.

Inventor： Jong Hee Kim ,  Hyun Joon Kim ,  Kyoung Ju Shin ,  Alexander Ward ,  Cheol-Gon Lee ,  Chong Chul Chai

IPC: G09G3/36 ,  H03K17/693

CPC classification number: H03K17/693 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/06

Abstract: A stage includes a first transistor including an input terminal to which a clock signal is applied and a control terminal connected to a first node; a first capacitor including terminals respectively connected to the first node and an output terminal of the first transistor; a second transistor including an input terminal connected to the output terminal of the first transistor, a control terminal connected to a second node, and an output terminal to which a low voltage is applied; a third transistor including an output terminal connected to the second node, a control terminal connected to the first node, and an input terminal to which the low voltage is applied; and a fourth transistor including an input terminal connected to the first node and an output terminal to which the low voltage is applied, wherein the fourth transistor is switched according to an output signal of a next stage.