公开(公告)号：US20160042694A1

公开(公告)日：2016-02-11

申请号：US14728844

申请日：2015-06-02

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Keun Lim ,  Hui-Won Yang ,  Chong-Chui Chai

IPC: G09G3/32

CPC classification number: G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2310/0251 ,  G09G2320/043

Abstract: A pixel circuit and an OLED display including the same are disclosed. The pixel circuit includes a driving transistor having a double gate structure, the driving transistor including a first gate electrode electrically connected to a first node, a second gate electrode electrically connected to a second node, a first electrode electrically connected to a first power supply voltage, and a second electrode electrically connected to the anode of the OLED. The pixel circuit also includes a switching transistor including a gate electrode configured to receive a scan signal, a first electrode configured to receive a data voltage, and a second electrode electrically connected to the first node. The pixel circuit further includes a storage capacitor and a compensation capacitor including a first electrode electrically connected to the second node and a second electrode electrically connected to the first electrode of the driving transistor.

Abstract translation: 公开了包括其的像素电路和OLED显示器。 像素电路包括具有双栅极结构的驱动晶体管，驱动晶体管包括与第一节点电连接的第一栅电极，与第二节点电连接的第二栅电极，电连接到第一电源电压的第一电极 以及与OLED的阳极电连接的第二电极。 像素电路还包括开关晶体管，其包括被配置为接收扫描信号的栅电极，被配置为接收数据电压的第一电极和与第一节点电连接的第二电极。 像素电路还包括存储电容器和包括电连接到第二节点的第一电极和电连接到驱动晶体管的第一电极的第二电极的补偿电容器。

公开(公告)号：US08816728B2

公开(公告)日：2014-08-26

申请号：US14057354

申请日：2013-10-18

Applicant: Samsung Display Co., Ltd.

Inventor： Soo-Wan Yoon ,  Yeong-Keun Kwon ,  Ji-Sun Kim ,  Young-Soo Yoon ,  Chong-Chui Chai

IPC: H03K3/00

CPC classification number: H03K3/012 ,  G09G3/3674 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/184 ,  G11C19/28

Abstract: A gate driving circuit includes a pull-up control part, a pull-up part, a carry part, a first pull-down part and a second pull-down part. The pull-up control part applies a carry signal from a previous stage to a first node. The pull-up part outputs an N-th gate output signal based on a clock signal. The carry part outputs an N-th carry signal based on the clock signal in response to the signal applied to the first node. The first pull-down part includes a plurality of transistors connected to each other in series. The first pull-down part pulls down a signal at the first node to a second off voltage in response to a carry signal of a next stage. The second pull-down part pulls down the N-th gate output signal to a first off voltage in response to the carry signal of the next stage.

Abstract translation: 栅极驱动电路包括上拉控制部分，上拉部分，携带部分，第一下拉部分和第二下拉部分。 上拉控制部分将来自前一级的进位信号应用于第一节点。 上拉部分基于时钟信号输出第N个栅极输出信号。 进位部分响应于施加到第一节点的信号，基于时钟信号输出第N个进位信号。 第一下拉部分包括彼此串联连接的多个晶体管。 第一下拉部分响应于下一级的进位信号将第一节点处的信号拉低至第二截止电压。 第二下拉部分响应于下一级的进位信号将第N栅极输出信号拉低至第一关断电压。