公开(公告)号：US20210335166A1

公开(公告)日：2021-10-28

申请号：US17181309

申请日：2021-02-22

Applicant: Samsung Display Co., Ltd.

Inventor： Sung Soo CHOI ,  Dae-Sik LEE ,  Ji Youn SEO ,  Gwang Soo AHN ,  Jong Jae LEE ,  Geun Hyuk CHOI

IPC: G09G3/00 ,  G09G3/20

Abstract: A power voltage generator includes a voltage sensor and a power controller. The voltage sensor is configured to sense a first voltage in a first charge sharing period of a gate clock signal and a second voltage in a second charge sharing period of the gate clock signal. The power breaker is configured to disconnect a power based on the first voltage and the second voltage.

公开(公告)号：US20160189654A1

公开(公告)日：2016-06-30

申请号：US14715792

申请日：2015-05-19

Applicant: Samsung Display Co., LTD.

Inventor： Yoon Ho KIM ,  Beom Jun KIM ,  Geun Hyuk CHOI ,  Noboru TAKEUCHI ,  Yong Soon LEE ,  Jong Hwan LEE ,  Hong-Woo LEE ,  Yong-Sik HWANG

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G09G3/3696 ,  G09G2310/08 ,  G09G2320/041 ,  G09G2320/043

Abstract: A display panel includes: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels; a gate driver connected to the plurality of gate lines to apply a gate signal voltage; a data driver connected to the plurality of data lines to apply a data voltage and a negative data voltage; and a gate voltage divider for generating a gate signal voltage including gate-on and gate-off voltages to provided it to the gate driver. The gate voltage divider adjusts the gate-off voltage in accordance with a driving time of the display panel and a temperature of the display panel.

Abstract translation: 显示面板包括：显示面板，包括多条栅极线，多条数据线和多个像素; 连接到所述多个栅极线以施加栅极信号电压的栅极驱动器; 连接到所述多条数据线的数据驱动器，以施加数据电压和负数据电压; 以及栅极分压器，用于产生包括栅极导通和栅极截止电压的栅极信号电压，以将其提供给栅极驱动器。 栅极分压器根据显示面板的驱动时间和显示面板的温度调节栅极截止电压。

公开(公告)号：US20170162123A1

公开(公告)日：2017-06-08

申请号：US15342530

申请日：2016-11-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Geun Hyuk CHOI ,  Sang Hyun LEE ,  Hyo Chul LEE ,  Jae Ho CHOI ,  Hyun Seok HONG

IPC: G09G3/3266 ,  G09G3/3291

CPC classification number: G09G3/3266 ,  G09G3/3291 ,  G09G2310/0286 ,  G09G2310/08

Abstract: A display device includes a timing controller which transmits a vertical clock signal having rising edges and falling edges to a gate driver and a gate driver which receives the vertical clock signal, to generate a first gate clock signal and a first inverted gate clock signal in accordance with one of the rising edges and the falling edges of the vertical clock signal, and to generate a second gate clock signal and a second inverted gate clock signal in accordance with a remaining one of the rising edges and the falling edges of the vertical clock signal.