公开(公告)号：US20210183913A1

公开(公告)日：2021-06-17

申请号：US16933801

申请日：2020-07-20

Applicant: Samsung Display Co., Ltd.

Inventor： Hong Beom Lee ,  Chang Woo Kwon

IPC: H01L27/12 ,  H01L21/3213 ,  H01L21/321

Abstract: A method of fabricating a thin-film transistor (TFT) array substrate including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a source electrode and a drain electrode comprising a plurality of metal layer patterns on the ohmic contact layer, in which the semiconductor layer, the ohmic contact layer, the source electrode and the drain electrode are formed through a single mask process, and one of the plurality of metal layer patterns is etched through a polishing process to form the source electrode and the drain electrode.

公开(公告)号：US09373647B2

公开(公告)日：2016-06-21

申请号：US14307705

申请日：2014-06-18

Applicant: Samsung Display Co., Ltd.

Inventor： Hong Beom Lee ,  Jun-Seok Lee

IPC: G02F1/1343 ,  G02F1/1368 ,  H01L27/12 ,  G02F1/1362 ,  G02F1/1337

CPC classification number: H01L27/124 ,  G02F1/1362 ,  G02F2001/133776

Abstract: A thin film transistor array panel includes: first to third gate lines extending in one direction and parallel to each other; a data line insulated from and intersecting the first to third gate lines; a first thin film transistor connected to the first gate line and the data line; a second thin film transistor connected to the second gate line and an output terminal of the first thin film transistor; a third thin film transistor connected to the third gate line and the data line; a fourth thin film transistor connected to the second gate line and an output terminal of the third thin film transistor; and first to fourth sub-pixel electrodes respectively connected to the first to fourth thin film transistors.

Abstract translation: 薄膜晶体管阵列面板包括：在一个方向上延伸并且彼此平行的第一至第三栅极线; 与第一至第三栅极线绝缘并与之相交的数据线; 连接到第一栅极线和数据线的第一薄膜晶体管; 连接到第二栅极线的第二薄膜晶体管和第一薄膜晶体管的输出端子; 连接到第三栅极线和数据线的第三薄膜晶体管; 连接到第二栅极线的第四薄膜晶体管和第三薄膜晶体管的输出端子; 以及分别连接到第一至第四薄膜晶体管的第一至第四子像素电极。