Abstract:
Disclosed is a display device, which includes a display panel, a controller that receives an image signal and an external synchronization signal and generates a control signal, and a driver that generates a driving signal in response the control signal and provides the driving signal to the display panel. The controller includes a synchronization signal generator that generates an internal synchronization signal based on a reference clock signal, a corrector that corrects the internal synchronization signal to generate a corrected synchronization signal, and a control signal generator that generates the control signal, and the control signal generator generates the control signal based on the external synchronization signal when the external synchronization signal is in a normal state, and generates the control signal based on the internal synchronization signal when the external synchronization signal is in an abnormal state.
Abstract:
Disclosed is a data driving circuit including a noise filter, first through third voltage generators, and an output circuit. The noise filter receives a driving voltage and removes noise from the driving voltage to output a filtered driving voltage. The first voltage generator outputs a first voltage, a second voltage, and a third voltage. The second voltage generator generates a first reference voltage based on the filtered driving voltage, the first voltage, and the second voltage. The third voltage generator generates a second reference voltage based on the filtered driving voltage, the second voltage, and the third voltage. The output circuit outputs a data signal of a voltage level corresponding to an image signal based on the first reference voltage and the second reference voltage.
Abstract:
A display device is disclosed. In one aspect, the display device includes a display panel including a plurality of pixels, and a data driver including a plurality of data output unit buffers electrically connected to a plurality of data lines electrically connected to the pixels. Each of the data output unit buffers includes an output terminal, a first transistor for applying a high level data voltage to the output terminal, and a second transistor for applying a low level data voltage to the output terminal. Each of the data output unit buffers also includes a first switch electrically connecting the first and second transistors to the output terminal, and a second switch electrically connecting a ground voltage to the output terminal.
Abstract:
A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.
Abstract:
A display apparatus includes a display panel, a data analyzer, a logic core and a latch. The display panel is configured to display an image. The data analyzer is configured to analyze input image data. The logic core is configured to compensate all of line data, compensate a part of the line data, or not compensate all of the line data according to an analysis result of the data analyzer. The latch is configured to receive compensated data from the logic core.
Abstract:
Exemplary embodiments of the present invention relate to a power supply of a display device that includes a driving circuit and a display panel that displays an image according to an output data voltage transmitted from the driving circuit. The power supply includes a first booster and a second booster provided in the driving circuit, the first booster generates a first output voltage supplied to an Op-amp of a source output circuit of the driving circuit, and the second booster generates a second output voltage supplied to buffers of the source output circuit of the driving circuit.
Abstract:
A display device is disclosed. In one aspect, the display device includes a display panel including a plurality of pixels, and a data driver including a plurality of data output unit buffers electrically connected to a plurality of data lines electrically connected to the pixels. Each of the data output unit buffers includes an output terminal, a first transistor for applying a high level data voltage to the output terminal, and a second transistor for applying a low level data voltage to the output terminal. Each of the data output unit buffers also includes a first switch electrically connecting the first and second transistors to the output terminal, and a second switch electrically connecting a ground voltage to the output terminal.
Abstract:
Disclosed is a data driving circuit including a noise filter, first through third voltage generators, and an output circuit. The noise filter receives a driving voltage and removes noise from the driving voltage to output a filtered driving voltage. The first voltage generator outputs a first voltage, a second voltage, and a third voltage. The second voltage generator generates a first reference voltage based on the filtered driving voltage, the first voltage, and the second voltage. The third voltage generator generates a second reference voltage based on the filtered driving voltage, the second voltage, and the third voltage. The output circuit outputs a data signal of a voltage level corresponding to an image signal based on the first reference voltage and the second reference voltage.
Abstract:
A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.
Abstract:
A power system for an organic light emitting diode (OLED) display includes a power supplier and a power source controller. The power supplier respectively supplies a first power source voltage and a second power source voltage to first and second power source voltage application lines. The power source controller calculates a reference power source voltage corresponding to a maximum average grayscale using a distribution for each grayscale of first to third image data, models each voltage drop of the first and second power source voltages for first to third subpixels, and reflects the voltage drop to the reference power source voltage to change the second power source voltage.