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公开(公告)号:US20180157134A1
公开(公告)日:2018-06-07
申请号:US15689710
申请日:2017-08-29
发明人: Yonghee LEE , Daesuk KIM , Kyungho KIM , Dong-Yoon LEE
IPC分类号: G02F1/1362 , G02F1/1368 , G02F1/1343 , H01L21/66 , H01L27/12
CPC分类号: G02F1/136259 , G02F1/134336 , G02F1/136286 , G02F1/1368 , G02F2001/136263 , G02F2201/123 , G09G3/20 , G09G2300/0426 , G09G2330/08 , G09G2330/10 , H01L22/22 , H01L27/124
摘要: A display panel includes gate lines, data lines, switching elements connected to the gate lines and the data lines, pixel electrodes connected to the switching elements and markers. The pixel electrode includes first, second third and fourth areas which are divided by a horizontal central line and a vertical central line. The first, second, third and fourth areas correspond to an upper-left portion, an upper-right portion, a lower-left portion and a lower-right portion of a central point of the pixel electrode. When the pixel electrode is disposed between first and second data lines and connected to the first data line, the marker is disposed in one of the first and third areas. When the pixel electrode is disposed between the first and second data lines and connected to the second data line, the marker is disposed in one of the second and fourth areas.
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公开(公告)号:US20210333607A1
公开(公告)日:2021-10-28
申请号:US17161418
申请日:2021-01-28
发明人: Dong Hee SHIN , Geunho LEE , Yonghee LEE
IPC分类号: G02F1/1345 , G09G3/36
摘要: A display apparatus includes: a display panel includes: a plurality of pixels to display an image; a gate driver to drive the pixels; a first part electrically connected to the pixels; and a second part electrically connected to the gate driver. The gate driver includes: a plurality of stages to generate a gate signal to be provided to the pixels; k number of clock wirings to provide k number of clock signals to the plurality of stages; and k number of clock bar wirings to provide k number of clock bar signals to the plurality of stages (where k is a natural number of one or greater), and the second part includes: k number of clock pads electrically connected to the k number of clock wirings, respectively; and k number of clock bar pads electrically connected to the k number of clock bar wirings, respectively. The k number of clock wirings and the k number of clock bar wirings are arranged in a first order, and the k number of clock pads and the k number of clock bar pads are arranged in a second order different from the first order.
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公开(公告)号:US20200249535A1
公开(公告)日:2020-08-06
申请号:US16853674
申请日:2020-04-20
发明人: Yonghee LEE , Daesuk KIM , Kyungho KIM , Dong-Yoon LEE
IPC分类号: G02F1/1362 , G02F1/1368 , G02F1/1343 , H01L21/66 , H01L27/12 , G09G3/20
摘要: A display panel includes gate lines, data lines, switching elements connected to the gate lines and the data lines, pixel electrodes connected to the switching elements and markers. The pixel electrode includes first, second third and fourth areas which are divided by a horizontal central line and a vertical central line. The first, second, third and fourth areas correspond to an upper-left portion, an upper-right portion, a lower-left portion and a lower-right portion of a central point of the pixel electrode. When the pixel electrode is disposed between first and second data lines and connected to the first data line, the marker is disposed in one of the first and third areas. When the pixel electrode is disposed between the first and second data lines and connected to the second data line, the marker is disposed in one of the second and fourth areas.
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