Display device
    1.
    发明授权

    公开(公告)号:US12185602B2

    公开(公告)日:2024-12-31

    申请号:US18437088

    申请日:2024-02-08

    Abstract: A display device comprises a substrate; a circuit array layer comprising pixel drivers, data lines, first dummy lines, and second dummy lines; and a light emitting array layer. The display area comprises middle, first side, and second side regions. The data lines comprise first, second, and third data lines disposed in the middle, first side, and second side regions, respectively. The first dummy lines comprise a first data detour line disposed in the first side region and adjacent to a part of the second data line, and auxiliary lines. The second dummy lines comprise a second data detour line configured to connect the first data detour line to the third data line, and additional lines. The auxiliary lines comprise a bias auxiliary line to which a bias power is applied; and a second power auxiliary line to which a second power is applied.

    Pixel and display device having a frame frequency with a plurality of non-emission periods

    公开(公告)号:US11741887B2

    公开(公告)日:2023-08-29

    申请号:US17745179

    申请日:2022-05-16

    CPC classification number: G09G3/32 G09G2300/0842 G09G2310/0278

    Abstract: A display device includes a pixel, a scan driver supplying first to third scan signals in a first non-emission period and supplying the second scan signal in a second non-emission period, an emission driver supplying an emission control signal in the first and second non-emission periods, and a data driver supplying a data signal in the first non-emission period. The pixel includes a light-emitting element, a first transistor, a second transistor connected between the data line and a second node, a first capacitor connected between the first and second nodes, a third transistor connected between a third power line and the first node, a storage capacitor connected between the first and third nodes, a fourth transistor connected between the third node and a fourth power line, a fifth transistor connected between the first power line and the first transistor, and a sixth transistor supplying a fifth supply voltage.

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