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公开(公告)号：US11837132B2
公开(公告)日：2023-12-05
申请号：US17500875
申请日：2021-10-13
发明人： Seong Joo Lee , Seok Tae Koh , Gyeong Gu Kang , Oh Jo Kwon , Hyun Sik Kim , Gyu Wan Lim , Keum Dong Jung
IPC分类号： G09G3/20
CPC分类号： G09G3/20 , G09G2300/0426 , G09G2300/0809 , G09G2300/0828 , G09G2310/0243 , G09G2310/0272 , G09G2310/0291 , G09G2310/08
摘要： An output buffer is disclosed that includes: a buffer circuit that outputs an output signal to an output terminal based on a first input signal provided to a first input terminal and a second input signal provided to a second input terminal; and a current supply circuit that is connected in parallel to the buffer circuit, and provides an auxiliary current to the output terminal based on the first input signal and the second input signal.
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公开(公告)号：US11721265B1
公开(公告)日：2023-08-08
申请号：US17985554
申请日：2022-11-11
发明人： Hyung Gun Ma , Gyu Wan Lim , Gyeong Gu Kang , Hyun Sik Kim , Keum Dong Jung , Moon Jae Jeong
IPC分类号： G09G3/20 , G06F3/044 , G09G3/3208 , H10K59/40
CPC分类号： G09G3/20 , G06F3/044 , G09G3/3208 , G09G2300/0828 , G09G2300/0852 , G09G2300/0871 , G09G2310/027 , G09G2310/0291 , G09G2330/028 , H10K59/40
摘要： A data driving circuit includes: a resistor string in which a plurality of resistors are connected in series; and a plurality of data channels connected to a high voltage node, intermediate voltage nodes, and a low voltage node of the resistor string and configured to convert a digital data signal into an analog data voltage. Each of the plurality of data channels includes: a main digital-to-analog converter connected to the high voltage node, the intermediate voltage nodes, and the low voltage node, a multiplier connected to an output terminal of the main digital-to-analog converter, a sub digital-to-analog converter connected to some of the high voltage node, the intermediate voltage nodes, and the low voltage node, and a voltage synthesizer connected to an output terminal of the multiplier and an output terminal of the sub digital-to-analog converter.
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公开(公告)号：US20230260441A1
公开(公告)日：2023-08-17
申请号：US17985554
申请日：2022-11-11
发明人： Hyung Gun Ma , Gyu Wan Lim , Gyeong Gu Kang , Hyun Sik Kim , Keum Dong Jung , Moon Jae Jeong
IPC分类号： G09G3/20
CPC分类号： G09G3/20 , H01L27/323
摘要： A data driving circuit includes: a resistor string in which a plurality of resistors are connected in series; and a plurality of data channels connected to a high voltage node, intermediate voltage nodes, and a low voltage node of the resistor string and configured to convert a digital data signal into an analog data voltage. Each of the plurality of data channels includes: a main digital-to-analog converter connected to the high voltage node, the intermediate voltage nodes, and the low voltage node, a multiplier connected to an output terminal of the main digital-to-analog converter, a sub digital-to-analog converter connected to some of the high voltage node, the intermediate voltage nodes, and the low voltage node, and a voltage synthesizer connected to an output terminal of the multiplier and an output terminal of the sub digital-to-analog converter.
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公开(公告)号：US12125426B2
公开(公告)日：2024-10-22
申请号：US18210960
申请日：2023-06-16
发明人： Hyung Gun Ma , Gyu Wan Lim , Gyeong Gu Kang , Hyun Sik Kim , Keum Dong Jung , Moon Jae Jeong
IPC分类号： G09G3/20 , G06F3/044 , G09G3/3208 , H10K59/40
CPC分类号： G09G3/20 , G06F3/044 , G09G3/3208 , G09G2300/0828 , G09G2300/0852 , G09G2300/0871 , G09G2310/027 , G09G2310/0291 , G09G2330/028 , H10K59/40
摘要： A data driving circuit includes: a resistor string in which a plurality of resistors are connected in series; and a plurality of data channels connected to a high voltage node, intermediate voltage nodes, and a low voltage node of the resistor string and configured to convert a digital data signal into an analog data voltage. Each of the plurality of data channels includes: a main digital-to-analog converter connected to the high voltage node, the intermediate voltage nodes, and the low voltage node, a multiplier connected to an output terminal of the main digital-to-analog converter, a sub digital-to-analog converter connected to some of the high voltage node, the intermediate voltage nodes, and the low voltage node, and a voltage synthesizer connected to an output terminal of the multiplier and an output terminal of the sub digital-to-analog converter.
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