公开(公告)号：US11462487B2

公开(公告)日：2022-10-04

申请号：US17001992

申请日：2020-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuseon Heo

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/10

Abstract: A semiconductor package includes a frame, a semiconductor chip, a through via, a connection pad, a lower redistribution layer on the bottom surfaces of the frame and the semiconductor chip, a connection terminal on the lower redistribution layer, an encapsulant covering the top surfaces of the frame and the semiconductor chip, and an upper redistribution layer on the encapsulant. The lower redistribution layer includes a lower insulating layer, a lower redistribution pattern, and an under-bump metal (UBM). The upper redistribution layer includes an upper insulating layer, an upper redistribution pattern, an upper via, and an upper connection pad. The lower insulating layer includes an inner insulating pattern surrounding the side surface of the UBM and an outer insulating pattern surrounding the side surface of the inner insulating pattern. The cyclization rate of the inner insulating pattern is higher than the cyclization rate of the outer insulating pattern.

公开(公告)号：US20240136332A1

公开(公告)日：2024-04-25

申请号：US18483545

申请日：2023-10-10

Applicant: Samsung Electronics Co., Ltd

Inventor： Yuseon Heo ,  Jihye Shim ,  Junhyeong Park

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/48106 ,  H01L2224/73215 ,  H01L2225/06527

Abstract: Provided is a method of manufacturing a semiconductor package, the method including forming a first wiring structure, forming a multi-layer photoresist on the first wiring structure, forming a plurality of openings in the multi-layer photoresist by exposing and developing the multi-layer photoresist, forming a plurality of conductive posts by forming a conductive material in the plurality of openings, removing the multi-layer photoresist, providing a semiconductor chip on the first wiring structure, forming an encapsulant on the semiconductor chip and the plurality of conductive posts, and forming a second wiring structure on the encapsulant, wherein the multi-layer photoresist includes at least two layers having different light transmittances.

公开(公告)号：US20240080994A1

公开(公告)日：2024-03-07

申请号：US18446544

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gun Lee ,  Junwoo Myung ,  Yuseon Heo

IPC: H05K3/46 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/465 ,  H05K1/0296 ,  H05K1/0306 ,  H05K1/114 ,  H05K3/0023 ,  H05K3/4661 ,  H05K3/4679 ,  H05K2201/09563 ,  H05K2201/096

Abstract: In fabricating a wiring structure, a first wiring is formed on a substrate. First and second light sensitive insulation layers that are reactive to light of first and second wavelength ranges, respectively, are sequentially formed on the first wiring. First and second exposing processes are performed using the light of the first and second wavelength ranges, respectively, to form first and second exposed portions in the first and second light sensitive insulation layers, respectively. The first and second exposed portions are removed by a developing process to form a hole and an opening, respectively. The hole and the opening extend through the first and second light sensitive insulation layers, respectively, to be connected to one another. A conductive layer is formed in the hole and in the opening, and is planarized to form a first via and a second wiring in the hole and in the opening, respectively.