公开(公告)号：US20190124765A1

公开(公告)日：2019-04-25

申请号：US16165743

申请日：2018-10-19

Applicant: IBIDEN CO., LTD.

Inventor： Takema Adachi ,  Toshihide Makino ,  Hidetoshi Noguchi

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/115 ,  H05K3/0038 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4644 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/09827 ,  H05K2203/0723 ,  H05K2203/107

Abstract: A printed wiring board includes: a core substrate having a core layer, conductor layers on the core layer, and through-hole conductors; a first build-up layer including an insulating layer on the substrate, an inner side conductor layer on the insulating layer, an outermost insulating layer on the inner side conductor layer, and an outermost conductor layer on the outermost insulating layer; and a second build-up layer including an insulating layer on the substrate, an inner side conductor layer on the insulating layer, an outermost insulating layer on the inner side conductor layer, and an outermost conductor layer on the outermost insulating layer. Each of the conductor layers, inner side conductor layers, and outermost conductor layers has a metal foil, a seed layer and an electrolytic plating film, and that each inner side conductor layer has the smallest thickness among the conductor layers, inner side conductor layers and outermost conductor layers.

公开(公告)号：US20180337134A1

公开(公告)日：2018-11-22

申请号：US15755935

申请日：2016-02-09

Applicant: HITACHI CHEMICAL COMPANY, LTD.

Inventor： Kazuyuki MITSUKURA ,  Masaya TOBA ,  Kenichi IWASHITA ,  Kohsuke URASHIMA ,  Kazuhiko KURAFUCHI

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4867 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2221/68386 ,  H01L2224/214 ,  H01L2224/73204 ,  H05K1/181 ,  H05K3/465 ,  H05K3/4682

Abstract: To provide a manufacturing method capable of manufacturing a high density semiconductor device excellent in transmission between chips at a favorable yield and at low cost. A method for manufacturing a semiconductor device includes an insulating layer forming step of forming an insulating layer 3 having a trench 4 above a substrate 1, a copper layer forming step of forming a copper layer 5a on the insulating layer 3 so as to fill the trench 4, and a removing step of removing the copper layer 5a on the insulating layer 3 by a fly cutting method so as to retain a copper layer part in the trench 4.

公开(公告)号：US09955590B2

公开(公告)日：2018-04-24

申请号：US14919343

申请日：2015-10-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chao-Fu Weng

IPC: H05K3/46 ,  H05K1/11 ,  H01L23/20 ,  H05K3/10 ,  H01L23/00

CPC classification number: H05K3/465 ,  H01L24/20 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/20 ,  H05K1/113 ,  H05K3/107 ,  H05K2201/09845 ,  H05K2201/10674 ,  H05K2203/1173 ,  H01L2924/014

Abstract: The present disclosure relates to redistribution layer structures useful in semiconductor substrate packages, semiconductor package structures, and chip structures. In an embodiment, a redistribution layer structure includes a dielectric layer, an anti-plating layer, and a conductive material. The dielectric layer defines one or more trenches. The conductive material is disposed in the trench(es), and the anti-plating layer is disposed on a surface of the dielectric layer.

公开(公告)号：US09693449B2

公开(公告)日：2017-06-27

申请号：US14655488

申请日：2013-12-20

Applicant: MITSUBISHI MATERIALS CORPORATION

Inventor： Shuji Nishimoto ,  Yoshiyuki Nagatomo

IPC: H05K1/00 ,  H05K1/02 ,  H01L23/373 ,  C04B37/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/46 ,  H05K7/14 ,  H01L23/42 ,  H05K3/00 ,  H01L23/473

CPC classification number: H05K1/0271 ,  C04B37/021 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/402 ,  C04B2237/407 ,  C04B2237/86 ,  H01L23/3735 ,  H01L23/42 ,  H01L23/473 ,  H01L2224/32225 ,  H05K1/0203 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/0061 ,  H05K3/248 ,  H05K3/32 ,  H05K3/465 ,  H05K7/14 ,  H05K2201/066 ,  H05K2201/09136

Abstract: A power module substrate includes an insulating layer, a circuit layer that is formed on a first surface of the insulating layer, and a metal layer that is formed on a second surface of the insulating layer, in which a first base layer is laminated on a surface of the metal layer on the opposite side of the surface to which the insulating layer is provided, and the first base layer has: a first glass layer that is formed at the interface with the metal layer; and a first Ag layer that is laminated on the first glass layer.

公开(公告)号：US09532467B2

公开(公告)日：2016-12-27

申请号：US14020104

申请日：2013-09-06

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H05K3/46 ,  H05K1/02 ,  H05K3/04 ,  H05K3/10

CPC classification number: H05K3/465 ,  H05K1/0298 ,  H05K3/045 ,  H05K3/108 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0554 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit substrate includes a base layer, a first patterned conductive layer, a dielectric layer, a conductive block and a second patterned conductive layer. The first patterned conductive layer is disposed on the base layer and has a first pad. The dielectric layer is disposed on the base layer and covers the first patterned conductive layer, wherein the dielectric layer has an opening and the first pad is exposed by the opening. The conductive block is disposed in the opening and covers the first pad. The second patterned conductive layer is disposed on a surface of the dielectric layer and has a second pad, wherein the second pad and the conductive block are integrally formed.

Abstract translation: 电路基板包括基底层，第一图案化导电层，电介质层，导电块和第二图案化导电层。 第一图案化导电层设置在基底层上并具有第一焊盘。 电介质层设置在基底层上并覆盖第一图案化导电层，其中电介质层具有开口，第一焊盘由开口露出。 导电块设置在开口中并覆盖第一焊盘。 第二图案化导电层设置在电介质层的表面上并具有第二焊盘，其中第二焊盘和导电块一体形成。

公开(公告)号：US20160366770A1

公开(公告)日：2016-12-15

申请号：US15186022

申请日：2016-06-17

Applicant: SONY CORPORATION

Inventor： Thomas MERKLE ,  Stefan KOCH ,  Joo-Young CHOI

IPC: H05K3/46 ,  H01L23/498 ,  H05K3/30 ,  H01L23/66 ,  H05K1/02 ,  H05K1/18 ,  H01L23/538

CPC classification number: H05K3/4697 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/66 ,  H01L25/16 ,  H01L2223/6616 ,  H01L2223/6633 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2924/0002 ,  H05K1/0243 ,  H05K1/16 ,  H05K1/185 ,  H05K3/301 ,  H05K3/465 ,  H05K2201/0715 ,  H05K2201/0723 ,  H05K2201/09972 ,  H05K2201/09981 ,  H05K2203/1469 ,  H01L2924/00

Abstract: The present invention relates to the field of integrating electronic systems that operate at mm-wave and THz frequencies. A monolithic multichip package, a carrier structure for such a package as well as manufacturing methods for manufacturing such a package and such a carrier structure are proposed to obtain a package that fully shields different functions of the mm-wave/THz system. The package is poured into place by polymerizing photo sensitive monomers. It gradually grows around and above the MMICs (Monolithically Microwave Integrated Circuit) making connection to the MMICs but recessing the high frequency areas of the chip. The proposed approach leads to functional blocks that are electromagnetically completely shielded. These units can be combined and cascaded according to system needs.

Abstract translation: 本发明涉及以毫米波和太赫兹频率工作的集成电子系统的领域。 提出了一种单片多芯片封装，这种封装的载体结构以及用于制造这种封装和这种载体结构的制造方法，以获得完全屏蔽mm波/ THz系统的不同功能的封装。 通过聚合光敏单体将包装倒入适当位置。 它逐渐在MMIC（单片微波集成电路）之上和之上增长，连接到MMIC，但使芯片的高频区域变得困难。 所提出的方法导致电磁完全屏蔽的功能块。 这些单元可以根据系统需要进行组合和级联。

公开(公告)号：US09491866B2

公开(公告)日：2016-11-08

申请号：US13809083

申请日：2011-07-07

Applicant: Sang Myung Lee ,  Byeong Ho Kim ,  Jin Su Kim ,  Myoung Hwa Nam ,  Yeong Uk Seo ,  Sung Woon Yoon

Inventor： Sang Myung Lee ,  Byeong Ho Kim ,  Jin Su Kim ,  Myoung Hwa Nam ,  Yeong Uk Seo ,  Sung Woon Yoon

IPC: H05K3/06 ,  H05K3/10 ,  H05K3/00 ,  H05K3/02 ,  H05K3/46 ,  H05K3/04

CPC classification number: H05K3/062 ,  H05K3/0026 ,  H05K3/0032 ,  H05K3/02 ,  H05K3/045 ,  H05K3/108 ,  H05K3/465 ,  H05K2203/0554 ,  H05K2203/0557 ,  Y10T29/49167

Abstract: Provided is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes preparing an insulation board, irradiating a laser onto a graytone mask to each a surface of the insulation board, thereby forming a circuit pattern groove and a via hole at the same time, and filling the circuit pattern groove and the via hole to form a buried circuit pattern and the via. Thus, the circuit pattern groove and the via hole may be formed using the graytone mask at the same time without perfolining a separate process for forming the via hole. Therefore, the manufacturing process may be simplified to reduce the manufacturing costs.

Abstract translation: 提供一种印刷电路板的制造方法。 制造印刷电路板的方法包括制备绝缘板，将激光照射到灰蒙蒙掩模到绝缘板的每个表面上，从而同时形成电路图案槽和通孔，并填充电路图案 沟槽和通孔形成掩埋电路图案和通孔。 因此，电路图案槽和通孔可以同时使用灰蒙版掩模形成，而不需要单独的用于形成通孔的工艺。 因此，可以简化制造过程以降低制造成本。

公开(公告)号：US09433107B2

公开(公告)日：2016-08-30

申请号：US14365920

申请日：2012-12-12

Applicant: LG INNOTEK CO., LTD.

Inventor： Hyun Seok Seo ,  Ki Do Chun ,  Sang Myung Lee ,  Yeong Uk Seo ,  Chang Woo Yoo ,  Byeong Ho Kim

IPC: H05K1/00 ,  H05K1/11 ,  H05K3/46 ,  H05K1/02 ,  H05K3/06 ,  H05K1/09

CPC classification number: H05K3/4644 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/06 ,  H05K3/465 ,  H05K2201/0376 ,  H05K2201/09781 ,  H05K2201/10204 ,  H05K2203/0353

Abstract: Provided is a printed circuit board, including a plurality of buried circuit patterns which are formed in an active area; and a plurality of buried dummy patterns which are uniformly formed in a dummy area except the active area. Thus, since when the circuit patterns are formed, the dummy patterns are also uniformly formed, a difference in plating can be reduced. Also, since the dummy patterns are uniformly formed in the dummy area, a difference in grinding between the dummy area and the active area can be reduced, thereby enabling the circuit patterns to be formed in the active area without the occurrence of over-grinding.

Abstract translation: 提供一种印刷电路板，包括形成在有源区域中的多个掩埋电路图案; 以及均匀地形成在除了有效区域之外的虚拟区域中的多个埋置的虚设图案。 因此，由于当形成电路图案时，也可以均匀地形成虚设图案，可以减少电镀差异。 此外，由于虚拟图案均匀地形成在虚拟区域中，所以可以减少虚设区域和有效区域之间的磨削差异，从而能够在有源区域中形成电路图案而不会发生过磨削。

公开(公告)号：US09313904B2

公开(公告)日：2016-04-12

申请号：US14310076

申请日：2014-06-20

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kentaro Kaneko ,  Katsuya Fukase

IPC: H05K1/09 ,  H05K3/46

CPC classification number: H05K3/465 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4679 ,  H05K2201/09527 ,  H05K2203/025

Abstract: A wiring board includes a first wiring layer including a first conductive layer and a second conductive layer coating a first surface and a side surface of the first conductive layer. A first insulating layer covers a first surface and a side surface of the second conductive layer so as to expose a second surface of the first conductive layer opposite to the first surface of the first conductive layer. A second wiring layer is stacked on a first surface of the first insulating layer and is electrically connected to the first wiring layer. The first surface and the side surface of the first conductive layer are smooth surfaces while the first surface and the side surface of the second conductive layer are roughened-surfaces.

Abstract translation: 布线基板包括第一布线层，第一布线层包括第一导电层和涂覆第一导电层的第一表面和侧表面的第二导电层。 第一绝缘层覆盖第二导电层的第一表面和侧表面，以暴露与第一导电层的第一表面相对的第一导电层的第二表面。 第二布线层堆叠在第一绝缘层的第一表面上并与第一布线层电连接。 第一导电层的第一表面和侧表面是平滑表面，而第二导电层的第一表面和侧表面是粗糙表面。

公开(公告)号：US09265161B2

公开(公告)日：2016-02-16

申请号：US12956545

申请日：2010-11-30

Applicant: Chi Hee Ahn ,  Sang Myung Lee ,  Yeong Uk Seo ,  Jin Su Kim ,  Sung Woon Yoon ,  Myoung Hwa Nam

Inventor： Chi Hee Ahn ,  Sang Myung Lee ,  Yeong Uk Seo ,  Jin Su Kim ,  Sung Woon Yoon ,  Myoung Hwa Nam

IPC: H05K3/02 ,  H05K3/10 ,  H05K3/46 ,  H05K3/18 ,  H05K3/00 ,  H05K3/04

CPC classification number: H05K3/465 ,  H05K3/0032 ,  H05K3/045 ,  H05K3/107 ,  H05K3/184 ,  H05K3/4661 ,  H05K2203/054 ,  Y10T29/49124 ,  Y10T29/49155

Abstract: An embedded PCB, a multi-layer PCB using the embedded PCB, and a method of manufacturing the same are provided. The method of manufacturing an embedded PCB includes a first step of patterning an insulating layer on which a photoresist layer is formed using a laser such that parts of the insulating layer are selectively etched to form a circuit pattern region and a second step of filling the circuit pattern region with a plating material to form a circuit pattern. Accordingly, the method of manufacturing an embedded PCB can simultaneously or sequentially etch a photoresist layer and an insulating layer using a laser to form a circuit pattern so as to obtain a micro pattern and simplify a manufacturing process and achieve alignment accuracy in construction of a multi-layer PCB using the embedded PCB to thereby improve product reliability and yield.

Abstract translation: 提供嵌入式PCB，使用嵌入式PCB的多层PCB及其制造方法。 制造嵌入式PCB的方法包括：使用激光使绝缘层图案化的第一步骤，使得绝缘层的一部分被选择性地蚀刻以形成电路图案区域;以及第二步骤， 图案区域与电镀材料形成电路图案。 因此，制造嵌入式PCB的方法可以使用激光器同时或顺序地蚀刻光致抗蚀剂层和绝缘层，以形成电路图案，从而获得微图案并简化制造工艺，并实现多层结构的对准精度 使用嵌入式PCB的PCB层，从而提高产品的可靠性和产量。