POWER GATE SWITCH ARCHITECTURE
    1.
    发明申请
    POWER GATE SWITCH ARCHITECTURE 有权
    电源门开关架构

    公开(公告)号:US20150145555A1

    公开(公告)日:2015-05-28

    申请号:US14267862

    申请日:2014-05-01

    Abstract: Inventive aspects include a method, apparatus, and system for reducing power switch cells in MTCMOS circuits. Such may include disposing columns of real and virtual power straps orthogonally over rows of logic cells. A first power switch cell can be disposed over a real and a virtual power strap in a first column, and collinear with a first row of logic cells. A second power switch cell can be disposed over a real a virtual power strap in a second column, and collinear with a fifth row of logic cells. A third power switch cell can be disposed over a real a virtual power strap in a third column, and collinear with a third row of logic cells. A fourth power switch cell can be disposed over a real a virtual power strap in a fourth column, and collinear with a seventh row of logic cells.

    Abstract translation: 发明方面包括用于减少MTCMOS电路中的功率开关单元的方法,装置和系统。 这样可以包括在逻辑单元的行上正交地布置实际和虚拟电源带的列。 第一电源开关单元可以布置在第一列中的真实和虚拟电源带上,并且与第一行逻辑单元共线。 第二电源开关单元可以布置在第二列中的实际虚拟电源带上,并且与第五行逻辑单元共线。 第三电源开关单元可以设置在第三列中的实际虚拟电源带上,并且与第三行逻辑单元共线。 第四电源开关单元可以布置在第四列中的实际虚拟电源带上,并且与第七行逻辑单元共线。

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