公开(公告)号：US20150145555A1

公开(公告)日：2015-05-28

申请号：US14267862

申请日：2014-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young KOOG ,  Revathi GOVINDARAJAN ,  Anil Kumar GUNDURAO

IPC: H03K17/16 ,  G06F17/50 ,  H03K19/177 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K17/161 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78 ,  G06F2217/82 ,  H03K19/0013 ,  H03K19/00315 ,  H03K19/177

Abstract: Inventive aspects include a method, apparatus, and system for reducing power switch cells in MTCMOS circuits. Such may include disposing columns of real and virtual power straps orthogonally over rows of logic cells. A first power switch cell can be disposed over a real and a virtual power strap in a first column, and collinear with a first row of logic cells. A second power switch cell can be disposed over a real a virtual power strap in a second column, and collinear with a fifth row of logic cells. A third power switch cell can be disposed over a real a virtual power strap in a third column, and collinear with a third row of logic cells. A fourth power switch cell can be disposed over a real a virtual power strap in a fourth column, and collinear with a seventh row of logic cells.

Abstract translation: 发明方面包括用于减少MTCMOS电路中的功率开关单元的方法，装置和系统。 这样可以包括在逻辑单元的行上正交地布置实际和虚拟电源带的列。 第一电源开关单元可以布置在第一列中的真实和虚拟电源带上，并且与第一行逻辑单元共线。 第二电源开关单元可以布置在第二列中的实际虚拟电源带上，并且与第五行逻辑单元共线。 第三电源开关单元可以设置在第三列中的实际虚拟电源带上，并且与第三行逻辑单元共线。 第四电源开关单元可以布置在第四列中的实际虚拟电源带上，并且与第七行逻辑单元共线。

公开(公告)号：US20150145122A1

公开(公告)日：2015-05-28

申请号：US14267872

申请日：2014-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young KOOG ,  Jiankang WANG ,  Harpreet GILL ,  Sunghwan MIN

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L23/495 ,  H01L23/522 ,  H01L2224/06133 ,  H01L2224/06135

Abstract: An embodiment includes an integrated circuit, comprising: a substrate; a first circuit formed on the substrate and coupled to a plurality of first pads on the substrate; and a second circuit formed on the substrate and coupled to a plurality of second pads on the substrate. The first pads are formed on a perimeter of the substrate; and the second pads extend from the perimeter of the substrate towards an interior of the substrate.

Abstract translation: 一个实施例包括集成电路，包括：衬底; 形成在所述衬底上并耦合到所述衬底上的多个第一焊盘的第一电路; 以及形成在所述衬底上并耦合到所述衬底上的多个第二焊盘的第二电路。 第一焊盘形成在衬底的周边上; 并且第二焊盘从衬底的周边延伸到衬底的内部。

公开(公告)号：US20150186585A1

公开(公告)日：2015-07-02

申请号：US14228232

申请日：2014-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Harish DANGAT ,  Young KOOG ,  Sarita BASWANT ,  Prasanth KODURI

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F2217/78

Abstract: An embodiment includes a method, comprising: receiving a layout of an integrated circuit having a plurality of regions; determining a utilization for each of the regions; for each region, selecting from among a plurality of switch cell organizations for the region in response to the corresponding utilization; and for each region, modifying the layout to include switch cells for the region according to the selected switch cell organization.

Abstract translation: 实施例包括一种方法，包括：接收具有多个区域的集成电路的布局; 确定每个区域的利用率; 对于每个区域，响应于相应的利用从所述区域的多个交换机组织中进行选择; 并且对于每个区域，根据所选择的交换机组织来修改布局以包括该区域的交换单元。