公开(公告)号：US20220036243A1

公开(公告)日：2022-02-03

申请号：US17147858

申请日：2021-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saptarsi Das ,  Sabitha Kusuma ,  Arnab Roy ,  Ankur Deshwal ,  Kiran Kolar Chandrasekharan ,  Sehwan Lee

IPC: G06N20/10 ,  G06F15/80 ,  G06F9/30 ,  G06F17/16

Abstract: An apparatus includes a global memory and a systolic array. The global memory is configured to store and provide an input feature map (IFM) vector stream from an IFM tensor and a kernel vector stream from a kernel tensor. The systolic array is configured to receive the IFM vector stream and the kernel vector stream from the global memory. The systolic array is on-chip together with the global memory. The systolic array includes a plurality of processing elements (PEs) each having a plurality of vector units, each of the plurality of vector units being configured to perform a dot-product operation on at least one IFM vector of the IFM vector stream and at least one kernel vector of the kernel vector stream per unit clock cycle to generate a plurality of output feature maps (OFMs).

公开(公告)号：US20240311009A1

公开(公告)日：2024-09-19

申请号：US18439092

申请日：2024-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Arnab Roy ,  Saptarsi Das ,  Kiran Kolar Chandrasekharan ,  Yeongon CHO

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0673

Abstract: Disclosed are a method of accessing a memory and an electronic device for performing the method. The electronic device includes a processor, and a memory electrically connected to the processor, wherein the processor may be configured to select a rank including bank groups of the memory, select a bank corresponding to a memory address to be accessed from among banks included in the selected rank, select a row and one or more columns from rows and columns of the selected bank corresponding to the memory address, and generate the memory address to access the memory based on an address mapping scheme according to the selected rank, the selected bank, the selected row, and the selected one or more columns.

公开(公告)号：US12039430B2

公开(公告)日：2024-07-16

申请号：US17098589

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Arnab Roy ,  Saptarsi Das ,  Ankur Deshwal ,  Kiran Kolar Chandrasek Haran ,  Sehwan Lee

IPC: G06N3/04 ,  G06F7/544 ,  G06N3/045

CPC classification number: G06N3/045 ,  G06F7/5443

Abstract: A method for computing an inner product on a binary data, a ternary data, a non-binary data, and a non-ternary data using an electronic device. The method includes calculating the inner product on a ternary data, designing a fused bitwise data path to support the inner product calculation on the binary data and the ternary data, designing a FPL data path to calculate an inner product between one of the non-binary data and the non-ternary data and one of the binary data and the ternary data, and distributing the inner product calculation for the binary data and the ternary data and the inner product between one of the non-binary data and the non-ternary data and one of the binary data and the ternary data in the fused bitwise data path and the FPL data path.