公开(公告)号：US20220036243A1

公开(公告)日：2022-02-03

申请号：US17147858

申请日：2021-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saptarsi Das ,  Sabitha Kusuma ,  Arnab Roy ,  Ankur Deshwal ,  Kiran Kolar Chandrasekharan ,  Sehwan Lee

IPC: G06N20/10 ,  G06F15/80 ,  G06F9/30 ,  G06F17/16

Abstract: An apparatus includes a global memory and a systolic array. The global memory is configured to store and provide an input feature map (IFM) vector stream from an IFM tensor and a kernel vector stream from a kernel tensor. The systolic array is configured to receive the IFM vector stream and the kernel vector stream from the global memory. The systolic array is on-chip together with the global memory. The systolic array includes a plurality of processing elements (PEs) each having a plurality of vector units, each of the plurality of vector units being configured to perform a dot-product operation on at least one IFM vector of the IFM vector stream and at least one kernel vector of the kernel vector stream per unit clock cycle to generate a plurality of output feature maps (OFMs).

公开(公告)号：US20240311009A1

公开(公告)日：2024-09-19

申请号：US18439092

申请日：2024-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Arnab Roy ,  Saptarsi Das ,  Kiran Kolar Chandrasekharan ,  Yeongon CHO

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0673

Abstract: Disclosed are a method of accessing a memory and an electronic device for performing the method. The electronic device includes a processor, and a memory electrically connected to the processor, wherein the processor may be configured to select a rank including bank groups of the memory, select a bank corresponding to a memory address to be accessed from among banks included in the selected rank, select a row and one or more columns from rows and columns of the selected bank corresponding to the memory address, and generate the memory address to access the memory based on an address mapping scheme according to the selected rank, the selected bank, the selected row, and the selected one or more columns.

公开(公告)号：US20210117755A1

公开(公告)日：2021-04-22

申请号：US17033132

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gopinath Vasanth Mahale ,  Pramod Parameshwara Udupa ,  Kiran Kolar Chandrasekharan ,  SEHWAN LEE

IPC: G06N3/04

Abstract: Disclosed is a hybrid traversal apparatus and method for a convolution neural network (CNN) accelerator architecture that receives input feature map (IFM) microbatches from a pixel memory and receiving kernel microbatches from a kernel memory, multiplies the IFM microbatches by the kernel microbatches while reusing the kernel microbatches based on a kernel reuse factor for at least one of a direct convolution (DConv) or a Winograd convolution (WgConv), to obtain output feature map (OFM) microbatches, and writes the generated OFM microbatches to the pixel memory, after quantization, non-linear function, and pooling on a result of the multiplying.

公开(公告)号：US11915118B2

公开(公告)日：2024-02-27

申请号：US18107210

申请日：2023-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saptarsi Das ,  Sabitha Kusuma ,  Sehwan Lee ,  Ankur Deshwal ,  Kiran Kolar Chandrasekharan

IPC: G06N3/04 ,  G06F17/16

CPC classification number: G06N3/04 ,  G06F17/16

Abstract: A method and an apparatus for processing layers in a neural network fetch Input Feature Map (IFM) tiles of an IFM tensor and kernel tiles of a kernel tensor, perform a convolutional operation on the IFM tiles and the kernel tiles by exploiting IFM sparsity and kernel sparsity, and generate a plurality of OFM tiles corresponding to the IFM tiles.

公开(公告)号：US11604958B2

公开(公告)日：2023-03-14

申请号：US16816861

申请日：2020-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saptarsi Das ,  Sabitha Kusuma ,  Sehwan Lee ,  Ankur Deshwal ,  Kiran Kolar Chandrasekharan

IPC: G06N3/04 ,  G06F17/16

Abstract: A method and an apparatus for processing layers in a neural network fetch Input Feature Map (IFM) tiles of an IFM tensor and kernel tiles of a kernel tensor, perform a convolutional operation on the IFM tiles and the kernel tiles by exploiting IFM sparsity and kernel sparsity, and generate a plurality of OFM tiles corresponding to the IFM tiles.