公开(公告)号：US20230240074A1

公开(公告)日：2023-07-27

申请号：US18129145

申请日：2023-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEONG-HUN JEONG ,  BYOUNGIL LEE ,  JOONHEE LEE

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor device includes a substrate including a lower horizontal layer and an upper horizontal layer and having a cell array region and a connection region, an electrode structure including electrodes, which are stacked above the substrate, and which extend from the cell array region to the connection region, a vertical channel structure on the cell array region that penetrates the electrode structure and is connected to the substrate, and a separation structure on the connection region that penetrates the electrode structure. The lower horizontal layer has a first top surface in contact with a first portion of the separation structure, and a second top surface in contact with a second portion of the separation structure, and an inflection point at which a height of the lower horizontal layer is abruptly changed between the first top surface and the second top surface.

公开(公告)号：US20210272981A1

公开(公告)日：2021-09-02

申请号：US17035970

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEONG-HUN JEONG ,  BYOUNGIL LEE ,  JOONHEE LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including a lower horizontal layer and an upper horizontal layer and having a cell array region and a connection region, an electrode structure including electrodes, which are stacked above the substrate, and which extend from the cell array region to the connection region, a vertical channel structure on the cell array region that penetrates the electrode structure and is connected to the substrate, and a separation structure on the connection region that penetrates the electrode structure. The lower horizontal layer has a first top surface in contact with a first portion of the separation structure, and a second top surface in contact with a second portion of the separation structure, and an inflection point at which a height of the lower horizontal layer is abruptly changed between the first top surface and the second top surface.

公开(公告)号：US20230337432A1

公开(公告)日：2023-10-19

申请号：US18340059

申请日：2023-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGWOO NAM ,  BYOUNGIL LEE ,  YUJIN SEO

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: 3D semiconductor memory devices may include a horizontal structure that may be on an upper surface of a substrate and may include first and second horizontal patterns sequentially stacked on the upper surface of the substrate, a stack structure including electrodes stacked on the horizontal structure, a vertical pattern extending through the electrodes and connected to the first horizontal pattern, and a separation structure intersecting the stack structure and the horizontal structure and protruding into the upper surface of the substrate. A lowermost electrode may have first inner sidewalls facing each other with the separation structure interposed therebetween. The second horizontal pattern may have second inner sidewalls facing each other with the separation structure interposed therebetween. A maximum distance between the first inner sidewalls in the first direction may be less than a maximum distance between the second inner sidewalls in the first direction.