公开(公告)号：US20240054276A1

公开(公告)日：2024-02-15

申请号：US18341142

申请日：2023-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUBIN KIM ,  JUNSU JEON ,  JAEHYUN KANG ,  BYUNGMOO KIM ,  JOONGWON JEON

IPC: G06F30/398 ,  G06F30/392 ,  G06F30/394

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F2119/18

Abstract: A method of manufacturing a semiconductor device includes designing a semiconductor device layout using a design rule manual (DRM), in which design rules are recorded, and performing failure evaluation of a failure including at least one gate structure failure of a semiconductor device manufactured using the designed semiconductor device layout. The method further includes updating the DRM by updating the design rules recorded in the DRM, based on a result of the failure evaluation, redesigning the semiconductor device layout using the updated DRM, and manufacturing the semiconductor device using the redesigned semiconductor device layout.

公开(公告)号：US20210064807A1

公开(公告)日：2021-03-04

申请号：US16859323

申请日：2020-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIN KIM ,  BYUNGMOO KIM ,  JAEHWAN KIM ,  JUNSU JEON

IPC: G06F30/392 ,  G06F30/398

Abstract: A method of designing a layout of a semiconductor device includes determining from among a plurality of integrated circuit (IC) blocks in the semiconductor device a selection IC block for which a layout is to be changed, changing an spacing interval at which fin structures included in the selection IC block are spaced apart from each other in a first direction from a first spacing interval to a second spacing interval, and determining in the selection IC block locations of source/drain regions connected to the fin structures spaced apart from each other in the first direction at the second spacing interval.