公开(公告)号：US20220310154A1

公开(公告)日：2022-09-29

申请号：US17685067

申请日：2022-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo MOON ,  Jihye KIM ,  Je Min RYU ,  Beomyong KIL ,  Sungoh AHN

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/18

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

公开(公告)号：US20230410891A1

公开(公告)日：2023-12-21

申请号：US18458743

申请日：2023-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo MOON ,  Jihye KIM ,  Je Min RYU ,  Beomyong KIL ,  Sungoh AHN

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/18

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

公开(公告)号：US20220199143A1

公开(公告)日：2022-06-23

申请号：US17690137

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo MOON ,  Beomyong KIL ,  Jihye KIM

IPC: G11C11/4074 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/409

Abstract: A memory device includes: first power pins in a first power area and configured to receive a first power voltage; data pins configured to transmit or receive data signals, the data pins being arranged in a first region and in a second region each including the first power area; control pins configured to transmit or receive control signals in the first region and in the second region; second power pins in a second power area between the first region and the second region and configured to receive a second power voltage different from the first power voltage; and ground pins in the second power area and configured to receive a ground voltage.

公开(公告)号：US20220083260A1

公开(公告)日：2022-03-17

申请号：US17245325

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haesuk LEE ,  Reum OH ,  Youngcheon KWON ,  Beomyong KIL ,  Jemin RYU ,  Jihyun CHOI

IPC: G06F3/06

Abstract: A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.

公开(公告)号：US20210343325A1

公开(公告)日：2021-11-04

申请号：US17130493

申请日：2020-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo MOON ,  Beomyong KIL ,  Jihye KIM

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/409 ,  G11C8/18

Abstract: A memory device includes: first power pins in a first power area and configured to receive a first power voltage; data pins configured to transmit or receive data signals, the data pins being arranged in a first region and in a second region each including the first power area; control pins configured to transmit or receive control signals in the first region and in the second region; second power pins in a second power area between the first region and the second region and configured to receive a second power voltage different from the first power voltage; and ground pins in the second power area and configured to receive a ground voltage.