公开(公告)号：US20210343325A1

公开(公告)日：2021-11-04

申请号：US17130493

申请日：2020-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo MOON ,  Beomyong KIL ,  Jihye KIM

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/409 ,  G11C8/18

Abstract: A memory device includes: first power pins in a first power area and configured to receive a first power voltage; data pins configured to transmit or receive data signals, the data pins being arranged in a first region and in a second region each including the first power area; control pins configured to transmit or receive control signals in the first region and in the second region; second power pins in a second power area between the first region and the second region and configured to receive a second power voltage different from the first power voltage; and ground pins in the second power area and configured to receive a ground voltage.

公开(公告)号：US20220310154A1

公开(公告)日：2022-09-29

申请号：US17685067

申请日：2022-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo MOON ,  Jihye KIM ,  Je Min RYU ,  Beomyong KIL ,  Sungoh AHN

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/18

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

公开(公告)号：US20220199143A1

公开(公告)日：2022-06-23

申请号：US17690137

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo MOON ,  Beomyong KIL ,  Jihye KIM

IPC: G11C11/4074 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/409

Abstract: A memory device includes: first power pins in a first power area and configured to receive a first power voltage; data pins configured to transmit or receive data signals, the data pins being arranged in a first region and in a second region each including the first power area; control pins configured to transmit or receive control signals in the first region and in the second region; second power pins in a second power area between the first region and the second region and configured to receive a second power voltage different from the first power voltage; and ground pins in the second power area and configured to receive a ground voltage.

公开(公告)号：US20250104751A1

公开(公告)日：2025-03-27

申请号：US18647853

申请日：2024-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo MOON ,  Jeonghyeok YOU ,  Seong-Ook JUNG ,  Ji Young KIM ,  Hohyun CHAE

IPC: G11C7/22 ,  G11C7/10 ,  G11C29/50

Abstract: A memory device includes core dies including memory cell arrays, and a buffer die electrically connected to the core dies through one or more through silicon vias. The buffer die includes a DQS generation circuit that receives an external clock signal from an external device and generates data strobe signals based on the external clock signal for communicating data with the core dies, a DQS calibration circuit that detects a latency of each of plural rank signal that are received from the core dies based on the data strobe signals, respectively, and a coefficient decision circuit that detects a threshold voltage code of the buffer die, applies a weight to the latency of each rank signal based on the threshold voltage code to generate a weighted calibration code for each rank signal, and transmits the weighted calibration codes to respective ones of the core dies.

公开(公告)号：US20230410891A1

公开(公告)日：2023-12-21

申请号：US18458743

申请日：2023-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo MOON ,  Jihye KIM ,  Je Min RYU ,  Beomyong KIL ,  Sungoh AHN

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/18

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

公开(公告)号：US20240078043A1

公开(公告)日：2024-03-07

申请号：US18242250

申请日：2023-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungmin KIM ,  Byongmo MOON

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0653 ,  G06F3/0673

Abstract: In some embodiments, a memory device includes a data sampler configured to sample a data signal based on a write data strobe signal, a measuring circuit configured to measure a temperature-based delay variation and a voltage-based delay variation of a transfer path of the write data strobe signal, a storage circuit configured to store a first coefficient code regulating a reference-based delay variation on the transfer path, a temperature sensor configured to sense the temperature of the transfer path, a monitoring circuit configured to generate a second coefficient code by comparing the sensed temperature, the temperature-based delay variation, the voltage-based delay variation, and the reference-based delay variation with each other, a reference voltage generator configured to generate a reference voltage, a voltage regulator configured to generate a regulation voltage, and a write data strobe signal transfer circuit configured to transfer the write data strobe signal to the data sampler.

公开(公告)号：US20220069822A1

公开(公告)日：2022-03-03

申请号：US17353917

申请日：2021-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo MOON ,  Jiyoung KIM ,  Seongook JUNG ,  Jongsoo LEE

IPC: H03K19/173 ,  H03K19/0175 ,  H03K19/017 ,  H03K19/17788 ,  G11C7/14 ,  G11C7/22

Abstract: A transmitter includes a multiplexer, control logic and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals and multi-phase clock signals. The plurality of input data signals are input in parallel. Each of the plurality of input data signals is a binary signal and has two voltage levels that are different from each other. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals based on the plurality of time-interleaved data signals. Each of the plurality of pull-up control signals has a voltage level that is temporarily boosted. The voltage mode driver generates an output data signal based on the at least one pull-down control signal and the plurality of pull-up control signals. The output data signal is a duobinary signal and has three voltage levels that are different from each other.

公开(公告)号：US20210225426A1

公开(公告)日：2021-07-22

申请号：US17084345

申请日：2020-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongmo MOON ,  Jihye Kim ,  Je Min Ryu ,  Beomyong Kil ,  Sungoh Ahn

IPC: G11C11/4093 ,  H01L25/18 ,  G11C11/4076 ,  G11C11/4096 ,  G06F3/06

Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.