公开(公告)号：US10950704B2

公开(公告)日：2021-03-16

申请号：US16441644

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jun Shin ,  Si-Wan Kim ,  Bong-Hyun Choi

IPC: H01L29/423 ,  H01L23/48 ,  H01L27/11582

Abstract: A vertical memory device includes a substrate including a cell array region and a staircase region surrounding the cell array region, gate electrodes on the cell array region and the staircase region, and a channel on the cell array region. The gate electrodes are isolated from each other in first and third directions and each extend in a second direction. The channel extends in the first direction through one or more gate electrodes. End portions in the second direction of first gate electrodes of the plurality of gate electrodes define first steps in the second direction and second steps in the third direction on the staircase region of the substrate, the second steps being connected to the first steps, respectively, at same levels.

公开(公告)号：US10930671B2

公开(公告)日：2021-02-23

申请号：US16514548

申请日：2019-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Bong-Hyun Choi

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/423 ,  H01L29/10 ,  H01L27/1157

Abstract: A vertical memory device includes a substrate having a cell array region and a staircase region. Gate electrodes are spaced apart from each other in first and third directions. A channel extends through the gate electrodes in the first direction on the cell array region. Each of the gate electrodes extends in a second direction. End portions in the second direction of one or more of the gate electrodes form a first stair structure on the staircase region of the substrate. The first stair structure includes first steps, a second step, and a third step sequentially disposed in the third direction. Each of the first steps has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length.