公开(公告)号：US10950704B2

公开(公告)日：2021-03-16

申请号：US16441644

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jun Shin ,  Si-Wan Kim ,  Bong-Hyun Choi

IPC: H01L29/423 ,  H01L23/48 ,  H01L27/11582

Abstract: A vertical memory device includes a substrate including a cell array region and a staircase region surrounding the cell array region, gate electrodes on the cell array region and the staircase region, and a channel on the cell array region. The gate electrodes are isolated from each other in first and third directions and each extend in a second direction. The channel extends in the first direction through one or more gate electrodes. End portions in the second direction of first gate electrodes of the plurality of gate electrodes define first steps in the second direction and second steps in the third direction on the staircase region of the substrate, the second steps being connected to the first steps, respectively, at same levels.

公开(公告)号：US11749326B2

公开(公告)日：2023-09-05

申请号：US17862718

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G06F3/06 ,  G06F13/16

CPC classification number: G11C8/06 ,  G06F3/06 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C7/1057

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US11715507B2

公开(公告)日：2023-08-01

申请号：US17387036

申请日：2021-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G06F3/06 ,  G06F13/16

CPC classification number: G11C8/06 ,  G06F3/06 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076 ,  G11C7/1057

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US10930671B2

公开(公告)日：2021-02-23

申请号：US16514548

申请日：2019-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Bong-Hyun Choi

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/423 ,  H01L29/10 ,  H01L27/1157

Abstract: A vertical memory device includes a substrate having a cell array region and a staircase region. Gate electrodes are spaced apart from each other in first and third directions. A channel extends through the gate electrodes in the first direction on the cell array region. Each of the gate electrodes extends in a second direction. End portions in the second direction of one or more of the gate electrodes form a first stair structure on the staircase region of the substrate. The first stair structure includes first steps, a second step, and a third step sequentially disposed in the third direction. Each of the first steps has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length.

公开(公告)号：US09472258B2

公开(公告)日：2016-10-18

申请号：US14970739

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jun Shin ,  Sung-Min Yim

IPC: G11C11/406 ,  G11C7/02

CPC classification number: G11C11/406 ,  G11C7/02 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4087 ,  G11C29/783

Abstract: A method of operating a memory device comprises receiving a first row address corresponding to a first word line in the first sub bank array and corresponding to a first word line in the second sub bank array, determining whether at least one of the first word lines has been replaced with a spare word line, (a) when neither of the first word lines has been replaced, receiving a first number of row addresses for refresh operations in order to refresh adjacent word lines to the first word lines, and (b) when at least one of the first word lines has been replaced with a spare word line, receiving a second number of row addresses for refresh operations in order to refresh adjacent word lines to any non-replaced first word and any spare word lines, wherein the second number is greater than the first number.

Abstract translation: 一种操作存储器件的方法包括：接收对应于第一子存储体阵列中的第一字线的第一行地址并对应于第二子存储体阵列中的第一字线，确定第一字线中的至少一个是否具有 被替换为备用字线，（a）当两个第一字线都没有被替换时，接收刷新操作的第一数量的行地址以便刷新与第一字线相邻的字线，以及（b）当 第一字线中的至少一个已被替换为备用字线，接收用于刷新操作的第二数量的行地址，以便将相邻字线刷新到任何未替换的第一字和任何备用字线，其中第二字线 数字大于第一个数字。

公开(公告)号：US12300353B2

公开(公告)日：2025-05-13

申请号：US18238232

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076

Abstract: A memory system, including a memory controller and a memory, wherein the memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller mixes a second command with the first command and transmits the mixture of the first command and the second command. The memory changes command latch timing depends on the first or second mode.

公开(公告)号：US11081152B2

公开(公告)日：2021-08-03

申请号：US16874916

申请日：2020-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C8/06 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G06F3/06 ,  G11C11/4076 ,  G06F13/16

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US10579263B2

公开(公告)日：2020-03-03

申请号：US16169178

申请日：2018-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G06F3/06 ,  G11C8/18 ,  G11C8/06 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G06F13/16

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US10930330B2

公开(公告)日：2021-02-23

申请号：US16717742

申请日：2019-12-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4076 ,  G06F13/16

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US10115448B2

公开(公告)日：2018-10-30

申请号：US15194784

申请日：2016-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ho Lee ,  Seung-Jun Shin ,  Tae-Young Oh

IPC: G11C11/406 ,  G06F3/06

Abstract: A memory device includes a memory bank including a plurality of memory blocks, a row selection circuit and a refresh controller. The row selection circuit is configured to perform an access operation and a refresh operation with respect to the memory bank. The refresh controller is configured to control the row selection circuit such that the memory device is operated selectively in an access mode or a self-refresh mode in response to a self-refresh command received from a memory controller, the refresh operation is performed in the access mode in response to an active command received from the memory controller and the refresh operation is performed in the self-refresh mode in response to at least one clock signal.