公开(公告)号：US20190018653A1

公开(公告)日：2019-01-17

申请号：US15649406

申请日：2017-07-13

申请人： International Business Machines Corporation

发明人： Tina Babinsky ,  Michael Klein ,  Cedric Lichtenau ,  Silvia M. Mueller

IPC分类号： G06F7/544 ,  G06F7/49 ,  G06F5/01

CPC分类号： G06F7/5443 ,  G06F5/01 ,  G06F7/49

摘要： Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

公开(公告)号：US10078813B1

公开(公告)日：2018-09-18

申请号：US15266477

申请日：2016-09-15

申请人： Harold T. Fogg

发明人： Harold T. Fogg

IPC分类号： G06F7/00 ,  G06Q10/08 ,  G06F17/30

CPC分类号： G06Q10/087 ,  G06F7/49 ,  G06F16/2272 ,  G06F16/258 ,  G06F17/10 ,  G06F17/12 ,  G06F17/16 ,  G06F17/18 ,  G06K19/06046 ,  G06Q10/08

摘要： A system is provided for providing a product and a location from a code selected from the group consisting of a product code index, a location code index, a location code value, and a product code value. The system comprises: a processor, an input coupled to the processor and configured to receive the code, a first converter operable to convert a product code index to a product code value; a second converter operable to convert a product code value to a location code value; a third converter operable to convert a location code index to a location code value; a fourth converter operable to convert a location code value to a product code value; whereby, a product and a location are provided.

公开(公告)号：US20160283196A1

公开(公告)日：2016-09-29

申请号：US14669288

申请日：2015-03-26

申请人： Altera Corporation

发明人： Martin Langhammer

IPC分类号： G06F7/49 ,  G06F7/501

CPC分类号： G06F7/49 ,  G06F7/501 ,  G06F7/5312

摘要： Circuitry accepting a first input value and a second input value, and outputting (a) a first sum involving the first input value and the second input value, and (b) a second sum involving the first input value and the second input value, includes a first adder circuit, a second adder circuit, a compressor circuit and a preprocessing stage. The first input value and the second input value are input to the first adder circuit to provide the first sum. The first input value and the second input value are input to the preprocessing stage to provide inputs to the compressor circuit, which provides first and second compressed output signals which in turn are input to the second adder circuit to provide the second sum. The preprocessing stage may include circuitry to programmably zero the first input value, so that the first sum is programmably settable to the second input value.

摘要翻译： 电路接受第一输入值和第二输入值，并且输出（a）涉及第一输入值和第二输入值的第一和，以及（b）涉及第一输入值和第二输入值的第二和，包括 第一加法器电路，第二加法器电路，压缩器电路和预处理级。 第一输入值和第二输入值被输入到第一加法器电路以提供第一和。 第一输入值和第二输入值被输入到预处理级以向压缩器电路提供输入，该压缩器电路提供第一和第二压缩输出信号，该压缩输出信号又被输入到第二加法器电路以提供第二和。 预处理阶段可以包括可编程地将第一输入值归零的电路，使得第一和可编程地设置为第二输入值。

公开(公告)号：US08975922B2

公开(公告)日：2015-03-10

申请号：US13235188

申请日：2011-09-16

申请人： Adrian Stoica ,  Radu Andrei ,  David Zhu ,  Mohammad Mehdi Mojarradi ,  Tuan A. Vo

发明人： Adrian Stoica ,  Radu Andrei ,  David Zhu ,  Mohammad Mehdi Mojarradi ,  Tuan A. Vo

IPC分类号： H03K19/094 ,  G06F7/00 ,  G06F7/49 ,  H03K19/00

CPC分类号： H03K19/0002 ,  G06F7/00 ,  G06F7/49 ,  H03K19/08

摘要： Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described.

摘要翻译： 使用N个大于2的N逻辑状态电平进行操作的电子逻辑门，以及操作这些门的方法。 电子逻辑门根据真值表进行操作。 至少两个具有可超过两个以上逻辑状态的逻辑状态的输入信号被提供给逻辑门。 每个逻辑门提供可以具有N个逻辑状态之一的输出信号。 所描述的门的示例包括具有两个输入A和B的NAND / NAND门和具有三个输入A，B和C的NAND / NAND门，其中A，B和C可以采取四种逻辑状态中的任一种。 描述使用这种门的系统，并且说明它们的操作。 还描述了使用N个逻辑状态级操作的光逻辑门。

公开(公告)号：US08513975B2

公开(公告)日：2013-08-20

申请号：US13541942

申请日：2012-07-05

申请人： Benjamin J. Cooper

发明人： Benjamin J. Cooper

IPC分类号： H03K19/00 ,  H03M7/34

CPC分类号： G06F7/49

摘要： Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.

摘要翻译： 提供了硬件和过程，用于有效解释多值信号。 多值信号具有用于指示多个数值或逻辑值的第一电压范围，以及用于提供控制功能的第二电压范围。 在一个示例中，多值电路被布置为可以级联在一起的一组行和列。 可以实现控制功能以使部分行，列或级联连接断电，从而节省电力并实现更有效的操作。

公开(公告)号：US20120268165A1

公开(公告)日：2012-10-25

申请号：US13541942

申请日：2012-07-05

申请人： Benjamin J. Cooper

发明人： Benjamin J. Cooper

IPC分类号： H03K19/02

CPC分类号： G06F7/49

摘要： Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.

摘要翻译： 提供了硬件和过程，用于有效解释多值信号。 多值信号具有用于指示多个数值或逻辑值的第一电压范围，以及用于提供控制功能的第二电压范围。 在一个示例中，多值电路被布置为可以级联在一起的一组行和列。 可以实现控制功能以使部分行，列或级联连接断电，从而节省电力并实现更有效的操作。

公开(公告)号：US07782089B2

公开(公告)日：2010-08-24

申请号：US12635307

申请日：2009-12-10

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： H03K19/00

CPC分类号： G06F7/49 ,  G06F17/5045 ,  G11C11/56 ,  H03K19/0002

摘要： N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.

公开(公告)号：US20090295430A1

公开(公告)日：2009-12-03

申请号：US12393562

申请日：2009-02-26

申请人： Adrian Stoica ,  Radu Andrei

发明人： Adrian Stoica ,  Radu Andrei

IPC分类号： H03K19/082 ,  G06F17/50

CPC分类号： H03K19/0002 ,  G06F7/00 ,  G06F7/49

摘要： A methodology for describing an input-output behavior of a multi-level logic gate to process simultaneously a multiplicity of independent Boolean logic functions, with each Boolean function processing signals carried on an individual, separate channel. An embodiment may simultaneously process the same data with the same function or with different functions, multiple data with the same function, or multiple data with different functions. In addition, multi-level logic signals (having more than two levels) may be processed, so that a higher communication bandwidth may be obtained without necessarily increasing the number of traces (wires). Other embodiments are described and claimed.

摘要翻译： 用于描述多级逻辑门的输入 - 输出行为的方法，以同时处理多个独立布尔逻辑函数，每个布尔函数处理单个信道上承载的信号。 实施例可以以相同的功能或具有不同功能，具有相同功能的多个数据或具有不同功能的多个数据同时处理相同的数据。 此外，可以处理多电平逻辑信号（具有多于两个电平），使得可以获得更高的通信带宽而不必增加迹线数量（线）。 描述和要求保护其他实施例。

公开(公告)号：US20090234900A1

公开(公告)日：2009-09-17

申请号：US12472731

申请日：2009-05-27

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： G06F17/10 ,  G06F7/38 ,  G06F7/52 ,  G06F7/50

CPC分类号： G06F7/49

摘要： Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are disclosed. Also an efficient method of processing large binary signals is disclosed.

摘要翻译： 公开了用于执行多值算术运算的装置和方法。 可以使用第一个真值表来添加，减去和乘以多值信号以生成残差和第二个真值表以生成进位。 另外，公开了在多值信号上有效执行功能a0b1 + a1b0的方法和装置。 还公开了一种处理大二进制信号的有效方法。

公开(公告)号：US07562106B2

公开(公告)日：2009-07-14

申请号：US11018956

申请日：2004-12-20

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： G06F15/00 ,  G06F7/52

CPC分类号： G06F7/49

摘要： Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are disclosed. Also an efficient method of processing large binary signals is disclosed.

摘要翻译： 公开了用于执行多值算术运算的装置和方法。 可以使用第一个真值表来添加，减去和乘以多值信号以生成残差和第二个真值表以生成进位。 另外，公开了在多值信号上有效执行功能a0b1 + a1b0的方法和装置。 还公开了一种处理大二进制信号的有效方法。