公开(公告)号：US20240057321A1

公开(公告)日：2024-02-15

申请号：US18338711

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daejin NAM ,  Boreum LEE ,  Kongsoo LEE ,  Sunguk JANG

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/485 ,  H10B12/02

Abstract: A semiconductor device may include a substrate including an active pattern, a conductive filling pattern on an impurity region at an upper portion of the active pattern, a first spacer and a second spacer stacked on a sidewall of the conductive filling pattern in a horizontal direction, and a bit line structure on the conductive filling pattern. The impurity region may include impurities. The horizontal direction may be parallel to an upper surface of the substrate. The first spacer may include an insulating material containing the impurities.