SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

    公开(公告)号:US20230141789A1

    公开(公告)日:2023-05-11

    申请号:US17864736

    申请日:2022-07-14

    CPC classification number: G11C11/40615 G11C11/4093 G11C11/40618

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

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