公开(公告)号：US20240249793A1

公开(公告)日：2024-07-25

申请号：US18394627

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin YOU ,  Eunae LEE ,  Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Kyomin SOHN

IPC: G11C29/52 ,  G11C11/406 ,  G11C11/408

CPC classification number: G11C29/52 ,  G11C11/40615 ,  G11C11/4085

Abstract: A memory controller manages a refresh. The memory controller is configured to communicate with a memory device including a memory cell array that include of a plurality of word lines may include a scheduler configured to control commands provided to the plurality of word lines, an error correction code engine that has a register including N entries and is configured to store, in the register, a first parameter which includes address information and active number information of N word lines among the plurality of word lines based on counting the number of actives of the plurality of word lines, a comparator configured to compare the first parameter with a threshold parameter, and a refresh management (RFM) decision circuit configured to determine refresh frequency of the plurality of word lines based on results output from the comparator and to generate an RFM command.

公开(公告)号：US20230141789A1

公开(公告)日：2023-05-11

申请号：US17864736

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Eunae LEE ,  Byeonggyu PARK ,  Yeonggeol SONG

IPC: G11C11/406 ,  G11C11/4093

CPC classification number: G11C11/40615 ,  G11C11/4093 ,  G11C11/40618

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

公开(公告)号：US20240201868A1

公开(公告)日：2024-06-20

申请号：US18588599

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US20210083687A1

公开(公告)日：2021-03-18

申请号：US16809949

申请日：2020-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijun LEE ,  Chanki KIM ,  Sunghye CHO ,  Myungkyu LEE

IPC: H03M13/11 ,  H03M13/15 ,  G06F17/16

Abstract: A memory controller configured to control a memory module, the memory controller including processing circuitry configured to perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome, determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and output a decoding status flag indicating the type of error.

公开(公告)号：US20210027830A1

公开(公告)日：2021-01-28

申请号：US16812850

申请日：2020-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangyun KIM ,  Younghun SEO ,  Hyejung KWON ,  Myungkyu LEE ,  Sunghye CHO

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/56 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an ECC engine, a voltage generator and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to word-lines and bit-lines, and a plurality of sense amplifiers to sense data stored in the plurality of memory cells. The ECC engine reads memory data from a target page of the memory cell array, performs an ECC decoding on the memory data, detects, based on the ECC decoding, an error in the memory data, and outputs error information associated with the error. The voltage generator provides driving voltages to the plurality of sense amplifiers, respectively. The control logic circuit controls the ECC engine, and controls the at least one voltage generator to increase an operating margin of each of the plurality of sense amplifiers based on error pattern information including the error information.

公开(公告)号：US20170102996A1

公开(公告)日：2017-04-13

申请号：US15288227

申请日：2016-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunyeong YU ,  Junjin KONG ,  Beom Kyu SHIN ,  Myungkyu LEE ,  Jiyoup KIM ,  Dongmin SHIN

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1092 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0683

Abstract: A redundant array of inexpensive disks (RAID) controller of a RAID storage system that includes one or more storage devices includes an error correction code (ECC) result manager configured to manage information of ECC result indicators when a data chunk that includes one or more ECC data units having an uncorrectable ECC error is read from among a plurality of data chunks dispersively stored in the one or more storage devices, each of the plurality of data chunks including a plurality of ECC data units, the ECC result indicators respectively indicating whether the plurality of ECC data units included in the plurality of data chunks has an uncorrectable ECC error; and an uncorrectable error counter configured to calculate a number of ECC result indicators indicating an uncorrectable ECC error among ECC result indicators corresponding to ECC data units having a same order in each of the plurality pluralit.y of data chunks.

公开(公告)号：US20230163786A1

公开(公告)日：2023-05-25

申请号：US17988140

申请日：2022-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Rae KIM ,  Kijun LEE ,  Myungkyu LEE ,  Sunghye CHO ,  Jin-Hoon JANG ,  Isak HWANG

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/09

CPC classification number: H03M13/1174 ,  H03M13/1575 ,  H03M13/098

Abstract: Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.

公开(公告)号：US20230146904A1

公开(公告)日：2023-05-11

申请号：US17984430

申请日：2022-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungkyu LEE ,  Kijun LEE ,  Sunghye CHO ,  Sungrae KIM

IPC: H03M13/15 ,  H03M13/00

CPC classification number: H03M13/159 ,  H03M13/611

Abstract: An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.

公开(公告)号：US20220382464A1

公开(公告)日：2022-12-01

申请号：US17743137

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

IPC: G06F3/06

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US20220139482A1

公开(公告)日：2022-05-05

申请号：US17326416

申请日：2021-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae KIM ,  Kijun LEE ,  Myungkyu LEE ,  Hoyoun KIM ,  Suhun LIM ,  Sunghye CHO

IPC: G11C29/42 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.