公开(公告)号：US20210012831A1

公开(公告)日：2021-01-14

申请号：US16813962

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihyuk Oh ,  Youngjin Park ,  Byoungjik Kim ,  Kiseok Park

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/14 ,  G11C29/44

Abstract: A memory device includes a plurality of memory chips for writing and reading data in response to a control command and an address signal, and a control logic circuit for transferring the control command and the address signal to the plurality of the memory chips, and receiving a first command from a memory controller to perform a first operation, different from a refresh operation, on at least one of a plurality of the memory chips. The control logic circuit, in response to a refresh command, transmits the first command to at least one of a plurality of the memory chips and performs the first operation during a pre-determined refresh time interval without carrying out the refresh operation.

公开(公告)号：US10978133B2

公开(公告)日：2021-04-13

申请号：US16813962

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihyuk Oh ,  Youngjin Park ,  Byoungjik Kim ,  Kiseok Park

IPC: G11C11/406 ,  G11C29/44 ,  G11C11/4093 ,  G11C29/14 ,  G11C11/4076

Abstract: A memory device includes a plurality of memory chips for writing and reading data in response to a control command and an address signal, and a control logic circuit for transferring the control command and the address signal to the plurality of the memory chips, and receiving a first command from a memory controller to perform a first operation, different from a refresh operation, on at least one of a plurality of the memory chips. The control logic circuit, in response to a refresh command, transmits the first command to at least one of a plurality of the memory chips and performs the first operation during a pre-determined refresh time interval without carrying out the refresh operation.