公开(公告)号：US20190109088A1

公开(公告)日：2019-04-11

申请号：US16200747

申请日：2018-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vincent Chun Fai LAU ,  Jung-ho DO ,  Byung-sung KIM ,  Chul-hong PARK

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/118 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

公开(公告)号：US20170221818A1

公开(公告)日：2017-08-03

申请号：US15493279

申请日：2017-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vincent Chun Fai LAU ,  Jung-ho DO ,  Byung-sung KIM ,  Chul-hong PARK

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.