公开(公告)号：US20200303374A1

公开(公告)日：2020-09-24

申请号：US16894045

申请日：2020-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deepak SHARMA ,  Hyun-jong LEE ,  Raheel AZMAT ,  Chul-hong PARK ,  Sang-jun PARK

IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

公开(公告)号：US20190326285A1

公开(公告)日：2019-10-24

申请号：US16453645

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sidharth RASTOGI ,  Subhash KUCHANURI ,  Raheel AZMAT ,  Pan-jae PARK ,  Chul-hong PARK ,  Jae-seok YANG ,  Kwan-young CHUN

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/49 ,  H01L29/06 ,  H01L23/535 ,  H01L21/768 ,  H01L21/76

Abstract: An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.

公开(公告)号：US20190221563A1

公开(公告)日：2019-07-18

申请号：US16363050

申请日：2019-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-hyuck CHOI ,  Hae-wang LEE ,  Hyoun-jee HA ,  Chul-hong PARK

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/535 ,  H01L23/528 ,  H01L29/08 ,  H01L23/522 ,  H01L29/06 ,  H01L29/66 ,  H01L29/45

Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

公开(公告)号：US20170221818A1

公开(公告)日：2017-08-03

申请号：US15493279

申请日：2017-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vincent Chun Fai LAU ,  Jung-ho DO ,  Byung-sung KIM ,  Chul-hong PARK

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

公开(公告)号：US20200294999A1

公开(公告)日：2020-09-17

申请号：US16887331

申请日：2020-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deepak SHARMA ,  Hyun-jong LEE ,  Raheel AZMAT ,  Chul-hong PARK ,  Sang-jun PARK

IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

公开(公告)号：US20190109088A1

公开(公告)日：2019-04-11

申请号：US16200747

申请日：2018-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vincent Chun Fai LAU ,  Jung-ho DO ,  Byung-sung KIM ,  Chul-hong PARK

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/118 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

公开(公告)号：US20170033101A1

公开(公告)日：2017-02-02

申请号：US15060829

申请日：2016-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deepak SHARMA ,  Hyun-jong LEE ,  Raheel AZMAT ,  Chul-hong PARK ,  Sang-jun PARK

IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/823828 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/6681

Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

Abstract translation: 提供了包括至少一个单元的集成电路，所述至少一个单元包括彼此间隔开的第一和第二有源区，设置在第一和第二有源区之间的虚拟区，设置在第一和第二有源区中的至少一个第一有源鳍 有源区并且在第一方向上延伸，在第二有源区的整个长度上沿着第一方向延伸的至少一个第二有源鳍，以及沿基本上垂直于第一方向的第二方向延伸的有源栅极线，其中 有源栅极线垂直地与第一有源区和虚拟区重叠，并且不垂直地与第二有源区重叠。

公开(公告)号：US20200335500A1

公开(公告)日：2020-10-22

申请号：US16920589

申请日：2020-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-hyuck CHOI ,  Hae-wang LEE ,  Hyoun-jee HA ,  Chul-hong PARK

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/08 ,  H01L23/535 ,  H01L23/522 ,  H01L29/45 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762 ,  H01L29/417 ,  H01L27/092

Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

公开(公告)号：US20190013314A1

公开(公告)日：2019-01-10

申请号：US15849030

申请日：2017-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-hyuck CHOI ,  Hae-wang LEE ,  Hyoun-jee HA ,  Chul-hong PARK

IPC: H01L27/088 ,  H01L29/06 ,  H01L23/528 ,  H01L29/08 ,  H01L23/535 ,  H01L23/522 ,  H01L29/45 ,  H01L21/8234 ,  H01L29/66

Abstract: An integrated circuit device may include a fin-type active region extending in a first direction on a substrate; an insulating separation structure extending in a second direction that intersects the first direction on the fin-type active region; a pair of split gate lines spaced apart from each other with the insulating separation structure therebetween and extending in the second direction to be aligned with the insulating separation structure; a pair of source/drain regions located on the fin-type active region and spaced apart from each other with the insulating separation structure therebetween; and a jumper contact located over the insulating separation structure and connected between the pair of source/drain regions.

公开(公告)号：US20180342462A1

公开(公告)日：2018-11-29

申请号：US15815083

申请日：2017-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Subhash KUCHANURI ,  Sidharth RASTOGI ,  Ranjan RAJEEV ,  Chul-hong PARK ,  Jae-seok YANG

IPC: H01L23/544 ,  H01L23/485 ,  G06F17/50 ,  H03K19/173

Abstract: An integrated circuit device includes: a pair of reference conductive lines arranged in parallel in a first direction in a first version logic cell and a pair of swap conductive lines arranged in parallel in a second version logic cell, wherein one reference conductive line and one swap conductive line in different wiring tracks of the pair of reference conductive lines and the pair of swap conductive lines have the same planar shape and the same length, and extend to intersect a cell boundary between the first version logic cell and the second version logic cell.